Ko, Chi Tung. / On t.p. "delta" and "sigma" appear as the Greek letters. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.1 / 摘要 --- p.3 / Acknowledgements --- p.4 / Table of Contents --- p.5 / List of Figures --- p.8 / List of Tables --- p.13 / Chapter Chapter 1 --- Introduction --- p.14 / Chapter 1.1 --- Motivation --- p.14 / Chapter 1.2 --- Objectives --- p.17 / Chapter 1.3 --- Organization of the Thesis --- p.17 / References --- p.18 / Chapter Chapter 2 --- Fundamentals of Delta-sigma Modulators --- p.20 / Chapter 2.1 --- Delta-sigma Modulator as a Feedback System --- p.20 / Chapter 2.2 --- Quantization Noise --- p.22 / Chapter 2.3 --- Oversampling --- p.23 / Chapter 2.4 --- Noise Shaping --- p.25 / Chapter 2.5 --- Performance Parameters --- p.27 / Chapter 2.6 --- Baseband Modulators vs Bandpass Modulators --- p.27 / Chapter 2.7 --- Discrete-time Modulators vs Continuous-time Modulators --- p.28 / Chapter 2.8 --- Single-bit Modulators vs Multi-bit Modulators --- p.29 / Chapter 2.9 --- Non-linearity and Image Problems in Multi-bit Delta-sigma Modulators --- p.29 / Chapter 2.9.1 --- Non-linearity Problem --- p.29 / Chapter 2.9.2 --- Image Problem --- p.31 / Reference --- p.36 / Chapter Chapter 3 --- Image Rejection and Non-linearity Suppression Techniques for Quadrature Multi-bit Δ¡♭ Modulators --- p.38 / Chapter 3.1 --- Quadrature DEM Technique --- p.38 / Chapter 3.1.1 --- Introduction and Working Principle --- p.38 / Chapter 3.1.2 --- Behavioral Simulation Results --- p.42 / Chapter 3.2 --- IQ DWA Technique --- p.44 / Chapter 3.2.1 --- Introduction and Working Principle --- p.44 / Chapter 3.2.2 --- Behavioral Simulation Results --- p.49 / Chapter 3.3 --- DWA and Bit-wise Data-Dependent DEM --- p.52 / Chapter 3.3.1 --- Introduction and Working Principle --- p.52 / Chapter 3.3.2 --- Behavioral Simulation Results --- p.54 / Chapter 3.4 --- Image Rejection Technique for Quadrature Mixer --- p.61 / Chapter 3.5 --- Conclusion --- p.63 / Reference --- p.64 / Chapter Chapter 4 --- System Design of a Multi-Bit CT Modulator for GSM/WCDMA Application --- p.65 / Chapter 4.1 --- Objective of Design and Design Specification --- p.65 / Chapter 4.2 --- Topology Selection --- p.65 / Chapter 4.3 --- Discrete-time Noise Transfer Function Generation --- p.66 / Chapter 4.4 --- Continuous-time Loop Filter Transfer Function Generation --- p.69 / Chapter 4.5 --- Behavioral Model of Modulator --- p.69 / Chapter 4.6 --- Dynamic Range Scaling --- p.75 / Chapter 4.7 --- Behavioral Modeling of Operational Amplifiers --- p.77 / Chapter 4.8 --- Impact of RC Variation on Performance --- p.85 / Chapter 4.9 --- Loop Filter Component Values --- p.88 / Chapter 4.10 --- Summary --- p.90 / Reference --- p.90 / Chapter Chapter 5 --- Transistor-level Implementation of Modulators --- p.92 / Chapter 5.1 --- Overview of Design --- p.92 / Chapter 5.2 --- Design of Operational Transconductance Amplifiers (OTAs) --- p.94 / Chapter 5.2.1 --- First Stage --- p.94 / Chapter 5.2.2 --- Second and Third Stages --- p.98 / Chapter 5.3 --- Design of Feed-forward Transconductance (Gm) Cells --- p.101 / Chapter 5.4 --- Design of Quantizer --- p.102 / Chapter 5.4.1 --- Reference Ladder Design --- p.102 / Chapter 5.4.2 --- Comparator Design --- p.104 / Chapter 5.5 --- Design of Feedback Digital-to-Analog Converter (DAC) --- p.106 / Chapter 5.5.1 --- DWA and DEM Logic --- p.107 / Chapter 5.5.2 --- DAC Circuit --- p.109 / Chapter 5.6 --- Design of Integrated Mixers --- p.111 / Chapter 5.7 --- Design of Clock Generators --- p.112 / Chapter 5.7.1 --- Master Clock Generator --- p.112 / Chapter 5.7.2 --- LO Clock Generator --- p.114 / Chapter 5.7.3 --- Simulation Results --- p.116 / Reference --- p.125 / Chapter Chapter 6 --- Physical Design of Modulators --- p.127 / Chapter 6.1 --- Floor Planning of Modulator --- p.127 / Chapter 6.2 --- Shielding of Sensitive Signals --- p.130 / Chapter 6.3 --- Common Centroid Layout --- p.130 / Chapter 6.4 --- Amplifier Layout --- p.132 / Reference --- p.137 / Chapter Chapter 7 --- Conclusions --- p.138 / Chapter 7.1 --- Conclusions --- p.138 / Chapter 7.2 --- Future Works --- p.138 / Appendix A Schematics of Building Blocks --- p.140 / First Stage Operational Amplifier --- p.140 / First Stage Amplifier Local Bias Circuit --- p.140 / Second and Third Stage Operational Amplifier --- p.141 / Second and Third Stage Local Bias Circuit --- p.141 / CMFB Circuit (First Stage) --- p.142 / CMFB Circuit (Second Stage) --- p.142 / Gm-Feed-forward Cells --- p.143 / Gm Feed-forward Cell Bias Circuit --- p.143 / Reference Ladder Circuit --- p.144 / Pre-amplifier Circuit --- p.145 / Latch Circuit --- p.145 / DAC Circuit (Unit Cell) --- p.146 / Author's Publications --- p.147

The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A switched-capacitor circuit contains operational amplifiers (opamps), capacitators, switches, and a clock generator. Capacitors are used to define the state variables of a system. They store charges for a defined time interval, and determine the state variables as voltage differences. Switches are used to direct the flow of charges and to enable the charging and discharging of capacitors. Nonoverlapping clock signals control the switches and allow charge transfer between the capacitors. Opamps are used in order to perform high-accuracy charge transfer from one capacitor to another. The goal of this research is to design and explore future low-voltage switched-capacitor circuits, which are crucial for portable devices. Low-voltage operation is needed for two reasons: making reliable and accurate systems compatible with the submicron CMOS technology and reducing power consumption of the digital circuits. To this end, three different switched-capacitor integrators are proposed, which function with very low supply voltages. One of these configurations is used to design a lowpass ����� modulator for digital-audio applications. This modulator is fabricated and tested demonstrating 80 dB dynamic range with a 1-V supply voltage. The second part of this research is to show that these low-voltage circuits are suitable for modern wireless communication applications, where the clock and signal frequencies are very high. This part of the research has focused on bandpass analog-to-digital converters. Bandpass analog-to-digital converters are among the key components in wireless communication systems. They are used to digitize the received analog signal at an intermediate center frequency. Such converters are used for digital FM or AM radio applications and for portable communication devices, such as cellular phones. The main block, in these converters, is the resonator, which is tuned to a particular center frequency. A resonator must be designed such that it has a sharp peak at a specific center frequency. However, because of circuit imperfections, the resonant peak gain and/or the center frequency are degraded in existing architectures. Two novel switched-capacitor resonators were invented during the second part of this research. These resonators demonstrate superior performance as compared to previous architectures. A fourth-order low-voltage bandpass ����� modulator, using one of these resonators, has been designed. / Graduation date: 2002

Delta-Sigma Modulator-based Analog-to-Digital converter design is an active area of research. New topologies require extensive simulations to verify their performance. A series of improvements were made to an existing circuit simulation package in order to speed the simulation process for the designer. Various examples of these improvements are presented in typical applications. / Graduation date: 1992

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Graduation date: 1996

The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.