<p>Multiplication is an important part of real-time system applications. Various hardware parallel multipliers used in such applications have been proposed. However, when the operand sizes of the multipliers and the process technology need to be changed, the existing multipliers have to be redesigned. </p><p>From the point of library cell reuse, this master thesis work aims at developing a module generator for parallel multipliers with the help of software programs. This generator can be used to create the gate-level schematic for fixed point two's complement number multipliers. Based on the generated schematic, the entire multiplier can be implemented by small manual intervention. This feature can reduce the time of chip design. </p><p>The design phases consist of the logic, circuit and physical designs. The logic design includes gate-level schematic generation with C and SKILL programs and structural VHDL-code descriptions as well as validation. The circuit and physical design are custom in Cadence and the routing uses automatic place and route tools. </p><p>To demonstrate the design method, an 18 by 18-bit modified Booth recoded multiplier was implemented in 0.18 µm CMOS process with a supply voltage of 1.2 V and simulated using simulator (Spectre). The number of integrated transistors is 13000 and the active area is 85000 µm². The postlayout simulation shows the critical path with a delay of 17 ns.</p>

Multiplication is an important part of real-time system applications. Various hardware parallel multipliers used in such applications have been proposed. However, when the operand sizes of the multipliers and the process technology need to be changed, the existing multipliers have to be redesigned. From the point of library cell reuse, this master thesis work aims at developing a module generator for parallel multipliers with the help of software programs. This generator can be used to create the gate-level schematic for fixed point two's complement number multipliers. Based on the generated schematic, the entire multiplier can be implemented by small manual intervention. This feature can reduce the time of chip design. The design phases consist of the logic, circuit and physical designs. The logic design includes gate-level schematic generation with C and SKILL programs and structural VHDL-code descriptions as well as validation. The circuit and physical design are custom in Cadence and the routing uses automatic place and route tools. To demonstrate the design method, an 18 by 18-bit modified Booth recoded multiplier was implemented in 0.18 µm CMOS process with a supply voltage of 1.2 V and simulated using simulator (Spectre). The number of integrated transistors is 13000 and the active area is 85000 µm2. The postlayout simulation shows the critical path with a delay of 17 ns.

<p>I digitala kretsar kan både bit-parallella och bit-seriella interface förekomma.T ex kan en integrerad digital krets (IC-krets) internt använda sig av bit-parallella aritmetiska kretsar medan dess kommunikation med andra integrerade kretsar sker bit-seriellt. Genom att använda seriell kommunikation mellan IC-kretsar kan antalet ben på kapslarna effektivt begränsas.</p><p>Detta examensarbete gick ut på att göra en layoutgenerator för generering av en parametriserbar serie/parallellomvandlare och en parallell/serieomvandlare. När en krets använder sig av både bit-seriell och bit-parallell representation av data behövs dessa för att omvandla mellan formaten.</p> / <p>In digital circuits both bit-parallel and bit-serial interfaces can occur. For example, an integrated digital circuit can use bit-parallel arithmetic circuits internally while its communication with other integrated circuits is bit serial. By using serial communication between IC:s the number of pins on the packages can be effectively limited. </p><p>The purpose of this final project work was to create a layout generator for generation of a parametrizable serial/parallel converter and a parallel/serial converter. If a circuit uses both bit-serial and bit-parallel representation of data these are needed to convert between the formats.</p>

I digitala kretsar kan både bit-parallella och bit-seriella interface förekomma.T ex kan en integrerad digital krets (IC-krets) internt använda sig av bit-parallella aritmetiska kretsar medan dess kommunikation med andra integrerade kretsar sker bit-seriellt. Genom att använda seriell kommunikation mellan IC-kretsar kan antalet ben på kapslarna effektivt begränsas. Detta examensarbete gick ut på att göra en layoutgenerator för generering av en parametriserbar serie/parallellomvandlare och en parallell/serieomvandlare. När en krets använder sig av både bit-seriell och bit-parallell representation av data behövs dessa för att omvandla mellan formaten. / In digital circuits both bit-parallel and bit-serial interfaces can occur. For example, an integrated digital circuit can use bit-parallel arithmetic circuits internally while its communication with other integrated circuits is bit serial. By using serial communication between IC:s the number of pins on the packages can be effectively limited. The purpose of this final project work was to create a layout generator for generation of a parametrizable serial/parallel converter and a parallel/serial converter. If a circuit uses both bit-serial and bit-parallel representation of data these are needed to convert between the formats.