It is thought that fast low cost computers can be built by employing large numbers of cheap microprocessors working together in a system. However increasing the number of microprocessors in a parallel computer system may not produce a linear increase in performance for general purpose programming. The problems seem to lie in the communication between processors and the method of exploiting parallelism. A multiprocessor system was constructed using six MC68000 microprocessors. The problems of communication and exploiting parallelism were tackled in the design of the multiprocessor system. The component processors in a multiprocessor system communicate with each other through a communication channel. It is essential that the communication hardware has a high bandwidth. A fast communication hardware was implemented based on a two port shared memory. One method of extracting parallelism in a computing problem is by using divide and conquer. A software system was developed that enables the multiprocessor to exploit parallelism derived by the divide and conquer method. A software kernel is employed to manage the scheduling of parallel tasks to processors and the communication between processors. The mode of computation is based on the demand driven model.

<p>During the recent years, computer performance has increased dramatically. To measure </p><p>the performance of computers, benchmarks are ideal tools. Benchmarks exist in many </p><p>areas and point to different applications. For instance, in a normal PC, benchmarks can be </p><p>used to test the performance of the whole system which includes the CPU, graphic card, </p><p>memory system, etc. For multiprocessor systems, there also exist open source benchmark </p><p>programs. In our project, we gathered information about some open benchmark programs </p><p>and investigated their applicability for evaluating embedded multiprocessor systems </p><p>intended for radar signal processing. During our investigation, parallel cluster systems </p><p>and embedded multiprocessor systems were studied. Two benchmark programs, HPL and </p><p>NAS Parallel Benchmark were identified as particularly relevant for the application field. </p><p>The benchmark testing was done on a parallel cluster system which has an architecture </p><p>that is similar to the architecture of embedded multiprocessor systems, used for radar </p><p>signal processing.</p>

During the recent years, computer performance has increased dramatically. To measure the performance of computers, benchmarks are ideal tools. Benchmarks exist in many areas and point to different applications. For instance, in a normal PC, benchmarks can be used to test the performance of the whole system which includes the CPU, graphic card, memory system, etc. For multiprocessor systems, there also exist open source benchmark programs. In our project, we gathered information about some open benchmark programs and investigated their applicability for evaluating embedded multiprocessor systems intended for radar signal processing. During our investigation, parallel cluster systems and embedded multiprocessor systems were studied. Two benchmark programs, HPL and NAS Parallel Benchmark were identified as particularly relevant for the application field. The benchmark testing was done on a parallel cluster system which has an architecture that is similar to the architecture of embedded multiprocessor systems, used for radar signal processing.

No description available.

No description available.

Reliability evaluation by analytic modelling constitute an important issue of designing a reliable multiprocessor system. In this thesis, a model for reliability and fault tolerance analysis of the interconnection network is presented, based on graph theory. Reliability and fault tolerance are considered as deterministic and probabilistic measures of connectivity. Exact techniques for reliability evaluation fail for large multiprocessor systems because of the enormous computational resources required. Therefore, approximation techniques have to be used. Three approaches are proposed, the first by simplifying the symbolic expression of reliability; the other two by applying a hierarchical decomposition to the system. All these methods give results close to those obtained by exact techniques.

Sistemas de Multiprocessados Embarcados são uma realidade, tanto no setor da indústria e quanto no setor acadêmico. Esses dispositivos oferecem capacidades de processamento paralelo objetivando cobrir requisitos cada vez maiores de aplicações complexas. A carga de trabalho subjacente das aplicações é suscetível a variação em tempo de execução o que, se não for tratada adequadamente, pode levar a degradação de eficiência em desempenho e energia. O aumento contínuo da complexidade da carga de trabalho das aplicações, bem como do tamanho dos sistemas multiprocessados emergentes, requer soluções de mapeamento dinâmicas e distribuídas. A maioria das técnicas de mapeamento propostas são implementações personalizadas, considerando um sistema operacional interno desenvolvido para uma arquitetura de processador específica. Essa prática restringe sua aplicação em outras plataformas, levando a um design extra, revalidação e, consequentemente, um custo oculto que pode ser um tanto quanto alto. Neste cenário, esta dissertação propõe a extensão do FreeRTOS para suportar mapeamento dinâmico e distribuído de tarefas em sistemas multiprocessados. O FreeRTOS tem portabilidade para mais de 30 arquiteturas de processadores embarcados, aumentando a portabilidade de software e reduzindo o tempo de desenvolvimento. A extensão proposta utiliza técnicas de mapeamento que permitem ao FreeRTOS atender a altas demandas de mapeamento de aplicações em tempo de execução. Outra contribuição deste trabalho é o desenvolvimento de um framework que permite a exploração de grandes sistemas fornecendo, simultaneamente, resultados para depuração. O framework proposto possibilita a geração automática de plataformas multiprocessadas considerando seu tamanho, a arquitetura do processador e um conjunto de aplicações. A descrição da plataforma resultante é altamente escalável permitindo extração de dados em tempo de execução e alta depuração. Estas características permitiram validar a extensão do FreeRTOS proposta em mais de uma arquitetura de processador da família ARM Cortex-M. Os casos de teste foram executados em plataformas de grande escala e em diferentes níveis de abstração com casos de mais de 120 aplicações incorporando mais de 600 tarefas processadas. Os resultados mostram que a extensão proposta apresenta resultados melhores ou iguais à literatura. / Embedded Multiprocessor systems are a reality, in both industry and academia sectors. Such devices offer parallel processing capabilities, aiming at covering the increasing requirements of complex applications. Underlying application workloads are susceptible to variation at runtime, which if not properly handled, may lead to the performance and power efficiency degradation. The continuous increase in the complexity of application workload and the size of emerging multiprocessor systems, calls for dynamic and distributed mapping solutions. The majority of the promoted mapping techniques are bespoke implementations, which consider an in-house operating system developed to a particular processor architecture. This practice restricts its adoption in other platforms, leading to extra design time, re-validation and, consequentially, a hidden cost that may well be quite high. In this scenario, this dissertation proposes a FreeRTOS extension that integrates the support to dynamic and distributed tasks mapping in multiprocessor systems. FreeRTOS is portable to more than 30 embedded processors architectures, increasing software portability and reducing development time. The proposed extension employs mapping techniques allowing FreeRTOS for handle high demands of application mapping in runtime. Another contribution of this work is the development of a framework, which enables the exploration of large systems while providing debugging facilities. The proposed framework provides the automatic generation of multiprocessor platforms, considering parameters of size, processor architecture, and an application set. The resulting platform description is high scalable while allows runtime data extraction and high debugging. These features allowed to validate the proposed FreeRTOS extension in more than one processor architecture from ARM Cortex-M family. Test cases were executed on large-scale platforms and at different levels of abstraction with cases of more than 120 applications incorporating more than 600 tasks processed. The results show that the proposed extension presents better or equal results to the literature.

Indian Institute of Science / workstations are ideally suited for computing jobs which require an interactive environment because they are basically single user machines and hence provide consistent response time. Another factor is the availability of many peripheral devices such as mice and light pens etc., which render workstations more user friendly for interactive jobs. However workstations are not suitable for highly compute intensive jobs as they are basically uniprocessor machines operating at moderate frequencies. For such type of work, large mainframes or supercomputers are more suitable, but interactive use of these machines is not economically feasible. Further more devices like mice etc., are not usually available for these types of machines. A typical application program is partly interactive and partly compute intensive and hence requires the features of workstations and supercomputers both. We have implemented a Cross Architecture Procedure call (CAPC) model. The purpose of this architecture is to make supercomputers available to workstation users as compute savers. In this method a workstation user marks some of the procedures in his/her application program which he/she wants to be executed on a remote mainframe or supercomputer connected to the workstation by a network. These procedures are compiled by a compiler to produce machine code for the computer on which they are supposed to be executed. A special purpose loader loads these procedures on the appropriate machines and then these procedures are executed on the remote machines at appropriate times without any further modification in the source code. Usually a user will want to execute compute intensive procedures on supercomputers and interactive parts on a workstation thus utilizing both the machines most efficiently. In our method both local and remote procedures use standard subroutine call instructions unlike RPC. In this architecture, both local and remote subroutines share a common virtual address space (physically distributed over many machines) and thus global and pointer variables can be used and parameters can be passed by reference with complete transparency. Arbitrary nesting of remote and local procedures is also possible. In our prototype implementation we have used an IBM - PC (8088 processor operating at 4.7 MHz) as a workstation and a MAGNUM - 1 (68030 processor operating at 25 MHz) as a compute server. As an IBM - PC does not have any virtual memory hardware (essential for our architecture) we have simulated a virtual memory management system for that machine through software, Our "network" is an RS 232C connection between the two machines using COTPL (Connection Oriented Transport. Provider for Local Communications) operating at 9600 baud. To test the system we have also implemented the required compiler for a simple language (a subset of Pascal - PL/OI which produces code for 8088 and 68030 machines, and also a special loader. The system has been completely implemented and tested with several programs. We have also made a thorough performance study of this system. The System is found to accelerate the applications as much as 2.8 times in the best cases.

Sistemas de Multiprocessados Embarcados são uma realidade, tanto no setor da indústria e quanto no setor acadêmico. Esses dispositivos oferecem capacidades de processamento paralelo objetivando cobrir requisitos cada vez maiores de aplicações complexas. A carga de trabalho subjacente das aplicações é suscetível a variação em tempo de execução o que, se não for tratada adequadamente, pode levar a degradação de eficiência em desempenho e energia. O aumento contínuo da complexidade da carga de trabalho das aplicações, bem como do tamanho dos sistemas multiprocessados emergentes, requer soluções de mapeamento dinâmicas e distribuídas. A maioria das técnicas de mapeamento propostas são implementações personalizadas, considerando um sistema operacional interno desenvolvido para uma arquitetura de processador específica. Essa prática restringe sua aplicação em outras plataformas, levando a um design extra, revalidação e, consequentemente, um custo oculto que pode ser um tanto quanto alto. Neste cenário, esta dissertação propõe a extensão do FreeRTOS para suportar mapeamento dinâmico e distribuído de tarefas em sistemas multiprocessados. O FreeRTOS tem portabilidade para mais de 30 arquiteturas de processadores embarcados, aumentando a portabilidade de software e reduzindo o tempo de desenvolvimento. A extensão proposta utiliza técnicas de mapeamento que permitem ao FreeRTOS atender a altas demandas de mapeamento de aplicações em tempo de execução. Outra contribuição deste trabalho é o desenvolvimento de um framework que permite a exploração de grandes sistemas fornecendo, simultaneamente, resultados para depuração. O framework proposto possibilita a geração automática de plataformas multiprocessadas considerando seu tamanho, a arquitetura do processador e um conjunto de aplicações. A descrição da plataforma resultante é altamente escalável permitindo extração de dados em tempo de execução e alta depuração. Estas características permitiram validar a extensão do FreeRTOS proposta em mais de uma arquitetura de processador da família ARM Cortex-M. Os casos de teste foram executados em plataformas de grande escala e em diferentes níveis de abstração com casos de mais de 120 aplicações incorporando mais de 600 tarefas processadas. Os resultados mostram que a extensão proposta apresenta resultados melhores ou iguais à literatura. / Embedded Multiprocessor systems are a reality, in both industry and academia sectors. Such devices offer parallel processing capabilities, aiming at covering the increasing requirements of complex applications. Underlying application workloads are susceptible to variation at runtime, which if not properly handled, may lead to the performance and power efficiency degradation. The continuous increase in the complexity of application workload and the size of emerging multiprocessor systems, calls for dynamic and distributed mapping solutions. The majority of the promoted mapping techniques are bespoke implementations, which consider an in-house operating system developed to a particular processor architecture. This practice restricts its adoption in other platforms, leading to extra design time, re-validation and, consequentially, a hidden cost that may well be quite high. In this scenario, this dissertation proposes a FreeRTOS extension that integrates the support to dynamic and distributed tasks mapping in multiprocessor systems. FreeRTOS is portable to more than 30 embedded processors architectures, increasing software portability and reducing development time. The proposed extension employs mapping techniques allowing FreeRTOS for handle high demands of application mapping in runtime. Another contribution of this work is the development of a framework, which enables the exploration of large systems while providing debugging facilities. The proposed framework provides the automatic generation of multiprocessor platforms, considering parameters of size, processor architecture, and an application set. The resulting platform description is high scalable while allows runtime data extraction and high debugging. These features allowed to validate the proposed FreeRTOS extension in more than one processor architecture from ARM Cortex-M family. Test cases were executed on large-scale platforms and at different levels of abstraction with cases of more than 120 applications incorporating more than 600 tasks processed. The results show that the proposed extension presents better or equal results to the literature.

Made available in DSpace on 2016-06-02T19:06:06Z (GMT). No. of bitstreams: 1 5351.pdf: 2740873 bytes, checksum: e4ce3a33279ffb7afccf2fc418af0f79 (MD5) Previous issue date: 2013-02-04 / During the last years we have witnessed a significant growing in the amount of data processed in a daily basis by companies, universities, and other institutions. Many use cases report processing of data volumes of petabytes in thousands of cores by a single application. MapReduce is a programming model, and a framework for the execution of applications which manipulate large data volumes in machines composed of thousands of processors/cores. Currently, Hadoop is the most widely adopted free implementation of MapReduce. Although there are reports in the literature about the use of MapReduce applications on platforms with more than one hundred cores, the scalability is not stressed and much remain to be studied in this field. One of the main challenges in the scalability study of MapReduce applications is the large number of configuration parameters of Hadoop. There are reports in the literature that mention more than 190 configuration parameters, 25 of which are known to impact the application performance in a significant way. In this work we study the scalability of MapReduce applications running on Hadoop. Due to the limited number of processors/cores available, we adopted a combined approach involving both experimentation and simulation. The experimentation has been carried out in a local cluster of 32 nodes, and for the simulation we have used MRSG (MapReduce Over SimGrid). In a first set of experiments, we identify the most impacting parameters in the performance and scalability of the applications. Then, we present a method for calibrating the simulator. With the calibrated simulator, we evaluated the scalability of one well-optimized application on larger clusters, with up to 10 thousands of nodes. / Durante os últimos anos, houve um significativo crescimento na quantidade de dados processados diariamente por companhias, universidades e outras instituições. Mapreduce é um modelo de programação e um framework para a execução de aplicações que manipulam grandes volumes de dados em máquinas compostas por milhares de processadores ou núcleos. Atualmente, o Hadoop é a implementação como software livre de Mapreduce mais largamente adotada. Embora existam relatos na literatura sobre o uso de aplicações Mapreduce em plataformas com cerca de quatro mil núcleos processando dados da ordem de dezenas de petabytes, o estudo dos limites de escalabilidade não foi esgotado e muito ainda resta a ser estudado. Um dos principais desafios no estudo de escalabilidade de aplicações Mapreduce é o grande número de parâmetros de configuração da aplicação e do ambiente Hadoop. Na literatura há relatos que mencionam mais de 190 parâmetros de configuração, sendo que 25 podem afetar de maneira significativa o desempenho da aplicação. Este trabalho contém um estudo sobre a escalabilidade de aplicações Mapreduce executadas na plataforma Hadoop. Devido ao número limitado de processadores disponíveis, adotou-se uma abordagem que combina experimentação e simulação. A experimentação foi realizada em um cluster local de 32 nós (com 64 processadores), e para a simulação empregou-se o simulador MRSG (MapReduce Over SimGrid). Como principais resultados, foram identificados os parâmetros de maior impacto no desempenho e na escalabilidade das aplicações. Esse resultado foi obtido por meio de simulação. Além disso, apresentou-se um método para a calibração do simulador MRSG, em função de uma aplicação representativa escolhida como benchmark. Com o simulador calibrado, avaliou-se a escalabilidade de uma aplicação bem otimizada. O simulador calibrado permitiu obter uma predição sobre a escalabilidade da aplicação para uma plataforma com até 10 mil nós.