In the past decade, aggressive scaling of transistor feature size has been a primary force driving higher Static Random Access Memory (SRAM) integration density. Due to the scaling, nanometer SRAM designs are getting more and more stability issues. The traditional way of analyzing stability is the Static Noise Margins (SNM). However, SNM has limited capability to capture critical nonlinearity, so it becomes incapable of characterizing the key dynamics of SRAM operations with induced soft-error. This thesis defines new stability margin metrics using a system-theoretic approach. Nonlinear system theories will be applied rigorously in this work to construct new stability concepts. Based on the phase portrait analysis, soft-error can be explained using bifurcation theory. The state flipping requires a minimum noise current (Icritical) and time (Tcritical). This work derives Icritical analytically for simple L1 model and provides design insight using a level one circuit model, and also provides numerical algorithms on both Icritical and Tcritial for higher a level device model. This stability analysis provides more physical characterization of SRAM noise tolerance property; thus has potential to provide needed yield estimation.

Jitter and noise on package and printed circuit board interconnects are limiting factors in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities (RPDs) is a major source of noise and jitter on the signal interconnects of these channels. Therefore, optimal design of the power delivery network (PDN) is required to reduce SSN induced noise and jitter and improve the performance of high speed channels. The design of PDN is done in frequency domain whereas jitter and noise are time domain events. As a result, multiple iterations between frequency domain design of PDN and time domain analysis of noise and jitter are required before a design is taped out. A new methodology to correlate PDN impedance with jitter and voltage margin is presented in this thesis. Using this methodology, it would be possible to estimate jitter and noise from the PDN impedance and reduce the iterations involved in freezing the PDN design. The SSN induced at a given RPD is proportional to the PDN impedance at that RPD. As a result, the jitter and the noise can be correlated to the PDN impedance. The PDN impedance is a function of frequency and has alternate local minima and local maxima at resonances and anti-resonances respectively. The anti-resonances in the PDN impedance at the RPD cause significant increase in the insertion loss of signal whose return current is disrupted at that RPD. The increase in the insertion loss attenuates significant harmonics of the signal degrading its rise/fall times and voltage levels. This results in reduction of timing and voltage margins of the signal. Thus, based on the insertion loss profile and harmonic content of the signal, an estimate of jitter and noise on the signal can be made. Passive test vehicles consisting of microstrips with RPDs have been designed and fabricated to demonstrate the proof of concept through both simulations and measurements. Suitable placement of decoupling capacitors is suggested to reduce the PDN impedance below the target impedance and to minimize coupling between two noise ports on the PDN. Genetic algorithm to optimize the selection and placement of decoupling capacitors has been implemented. The efficacy of the algorithm has been demonstrated by testing it on a power delivery networks consisting of a simple power/ground plane pair.

Technology scaling has been the most obvious choice of designers and chip manufacturing companies to improve the performance of analog and digital circuits. With the ever shrinking technological node, process variations can no longer be ignored and play a significant role in determining the performance of nanoscaled devices. By choosing a worst case design methodology, circuit designers have been very munificent with the design parameters chosen, often manifesting in pessimistic designs with significant area overheads. Significant work has been done in estimating the impact of intra-die process variations on circuit performance, pertinently, noise margin and standby leakage power, for fixed transistor channel dimensions. However, for an optimal, high yield, SRAM cell design, it is absolutely imperative to analyze the impact of process variations at every design point, especially, since the distribution of process variations is a statistically varying parameter and has an inverse correlation with the area of the MOS transistor. Furthermore, the first order analytical models used for optimization of SRAM memories are not as accurate and the impact of voltage and its inclusion as an input, along with other design parameters, is often ignored. In this thesis, the performance parameters of a nano-scaled 6-T SRAM cell are modeled as an accurate, yield aware, empirical polynomial predictor, in the presence of intra-die process variations. The estimated empirical models are used in a constrained non-linear, robust optimization framework to design an SRAM cell, for a 45 nm CMOS technology, having optimal performance, according to bounds specified for the circuit performance parameters, with the objective of minimizing on-chip area. This statistically aware technique provides a more realistic design methodology to study the trade off between performance parameters of the SRAM. Furthermore, a dual optimization approach is followed by considering SRAM power supply and wordline voltages as additional input parameters, to simultaneously tune the design parameters, ensuring a high yield and considerable area reduction. In addition, the cell level optimization framework is extended to the system level optimization of caches, under both cell level and system level performance constraints.

No description available.

Aggressive scaling of CMOS technology in sub-90nm nodes has created huge challenges. Variations due to fundamental physical limits, such as random dopants fluctuation (RDF) and line edge roughness (LER) are increasing significantly with technology scaling. In addition, manufacturing tolerances in process technology are not scaling at the same pace as transistor's channel length due to process control limitations (e.g., sub-wavelength lithography). Therefore, within-die process variations worsen with successive technology generations. These variations have a strong impact on the maximum clock frequency and leakage power for any digital circuit, and can also result in functional yield losses in variation-sensitive digital circuits (such as SRAM). Moreover, in nanometer technologies, digital circuits show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost while achieving higher performance and density. It is therefore not surprising that the International Technology Roadmap for Semiconductors (ITRS) lists variability as one of the most challenging obstacles for IC design in nanometer regime. To facilitate variation-tolerant design, we study the impact of random variations on the delay variability of a logic gate and derive simple and scalable statistical models to evaluate delay variations in the presence of within-die variations. This work provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, especially at lower supply voltages. The derived models are simple, scalable, bias dependent and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit/architecture optimization as well as technology prediction (especially in low-power and low-voltage operation). The derived models are verified using Monte Carlo SPICE simulations using industrial 90nm technology. Random variations in nanometer technologies are considered one of the largest design considerations. This is especially true for SRAM, due to the large variations in bitcell characteristics. Typically, SRAM bitcells have the smallest device sizes on a chip. Therefore, they show the largest sensitivity to different sources of variations. With the drastic increase in memory densities, lower supply voltages and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. In this research, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow accounts for the impact of bitcell read current variation, sense amplifier offset distribution, timing window variation and leakage variation on functional yield. The methodology overcomes the pessimism existing in conventional worst-case design techniques that are used in SRAM design. The proposed statistical yield estimation methodology allows early yield prediction in the design cycle, which can be used to trade off performance and power requirements for SRAM. The methodology is verified using measured silicon yield data from a 1Mb memory fabricated in an industrial 45nm technology. Embedded SRAM dominates modern SoCs and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, in the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operation and meet yield targets. We propose a new architecture that significantly reduces array switching power for SRAM. The proposed architecture combines built-in self-test (BIST) and digitally controlled delay elements to reduce the wordline pulse width for memories while ensuring correct read operation; hence, reducing switching power. A new statistical simulation flow was developed to evaluate the power savings for the proposed architecture. Monte Carlo simulations using a 1Mb SRAM macro from an industrial 45nm technology was used to examine the power reduction achieved by the system. The proposed architecture can reduce the array switching power significantly and shows large power saving - especially as the chip level memory density increases. For a 48Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it a very attractive solution for 45nm and below technologies. In addition to its impact on bitcell read current, the increase of local variations in nanometer technologies strongly affect SRAM cell stability. In this research, we propose a novel single supply voltage read assist technique to improve SRAM static noise margin (SNM). The proposed technique allows precharging different parts of the bitlines to VDD and GND and uses charge sharing to precisely control the bitline voltage, which improves the bitcell stability. In addition to improving SNM, the proposed technique also reduces memory access time. Moreover, it only requires one supply voltage, hence, eliminates the need of large area voltage shifters. The proposed technique has been implemented in the design of a 512kb memory fabricated in 45nm technology. Results show improvements in SNM and read operation window which confirms the effectiveness and robustness of this technique.

Aggressive scaling of CMOS technology in sub-90nm nodes has created huge challenges. Variations due to fundamental physical limits, such as random dopants fluctuation (RDF) and line edge roughness (LER) are increasing significantly with technology scaling. In addition, manufacturing tolerances in process technology are not scaling at the same pace as transistor's channel length due to process control limitations (e.g., sub-wavelength lithography). Therefore, within-die process variations worsen with successive technology generations. These variations have a strong impact on the maximum clock frequency and leakage power for any digital circuit, and can also result in functional yield losses in variation-sensitive digital circuits (such as SRAM). Moreover, in nanometer technologies, digital circuits show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost while achieving higher performance and density. It is therefore not surprising that the International Technology Roadmap for Semiconductors (ITRS) lists variability as one of the most challenging obstacles for IC design in nanometer regime. To facilitate variation-tolerant design, we study the impact of random variations on the delay variability of a logic gate and derive simple and scalable statistical models to evaluate delay variations in the presence of within-die variations. This work provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, especially at lower supply voltages. The derived models are simple, scalable, bias dependent and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit/architecture optimization as well as technology prediction (especially in low-power and low-voltage operation). The derived models are verified using Monte Carlo SPICE simulations using industrial 90nm technology. Random variations in nanometer technologies are considered one of the largest design considerations. This is especially true for SRAM, due to the large variations in bitcell characteristics. Typically, SRAM bitcells have the smallest device sizes on a chip. Therefore, they show the largest sensitivity to different sources of variations. With the drastic increase in memory densities, lower supply voltages and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. In this research, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow accounts for the impact of bitcell read current variation, sense amplifier offset distribution, timing window variation and leakage variation on functional yield. The methodology overcomes the pessimism existing in conventional worst-case design techniques that are used in SRAM design. The proposed statistical yield estimation methodology allows early yield prediction in the design cycle, which can be used to trade off performance and power requirements for SRAM. The methodology is verified using measured silicon yield data from a 1Mb memory fabricated in an industrial 45nm technology. Embedded SRAM dominates modern SoCs and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, in the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operation and meet yield targets. We propose a new architecture that significantly reduces array switching power for SRAM. The proposed architecture combines built-in self-test (BIST) and digitally controlled delay elements to reduce the wordline pulse width for memories while ensuring correct read operation; hence, reducing switching power. A new statistical simulation flow was developed to evaluate the power savings for the proposed architecture. Monte Carlo simulations using a 1Mb SRAM macro from an industrial 45nm technology was used to examine the power reduction achieved by the system. The proposed architecture can reduce the array switching power significantly and shows large power saving - especially as the chip level memory density increases. For a 48Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it a very attractive solution for 45nm and below technologies. In addition to its impact on bitcell read current, the increase of local variations in nanometer technologies strongly affect SRAM cell stability. In this research, we propose a novel single supply voltage read assist technique to improve SRAM static noise margin (SNM). The proposed technique allows precharging different parts of the bitlines to VDD and GND and uses charge sharing to precisely control the bitline voltage, which improves the bitcell stability. In addition to improving SNM, the proposed technique also reduces memory access time. Moreover, it only requires one supply voltage, hence, eliminates the need of large area voltage shifters. The proposed technique has been implemented in the design of a 512kb memory fabricated in 45nm technology. Results show improvements in SNM and read operation window which confirms the effectiveness and robustness of this technique.

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Although scalingof CMOS technology has been predicted to continue for another decade, novel technological solutions are required to overcome the fundamental limitations of the decananometer MOS transistors. Single Electron Transistor (SET) has attracted attention mainly because of its unique Coulomb blockade oscillations characteristics, ultra low power dissipation and nanoscale feature size. Despite the high potential, due to some intrinsic limitations (e.g., very low current drive) it will be very difficult for SET to compete head-to-head with CMOS’s large-scale infrastructure, proven design methodologies, and economic predictability. Nevertheless, the characteristics of SET and MOS transistors are quite complementary. SET advocates low-power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages like high-speed driving and voltage gain that can compensate the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single-electronics is unlikely in the near future, it is also true that combining SET and CMOS one can bring out new functionalities, which are unmirrored in pure CMOS technology. As the hybridization of CMOSand SET is gaining popularity, silicon SETs are appearing to be more promising than metallic SETs for their possible integration with CMOS. SETs are normally studied on the basis of the classical Orthodox Theory, where quantization of energy states in the island is completely ignored. Though this assumption greatly simplifies the physics involved, it is valid only when the SET is made of metallic island. As one cannot neglect the quantization of energy states in a semi conductive island, it is extremely important to study the effects of energy quantization on hybrid CMOSSET integrated circuits. The main objectives of this thesis are: (1) understand energy quantization effects on SET by numerical simulations; (2) develop simple analytical models that can capture the energy quantization effects; (3)analyze the effects of energy quantization on SET logic inverter, and finally; (4)developa CAD framework for CMOS-SETco-simulation and to study the effects of energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effects of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states.It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. Anew model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termedas “Quantization Threshold”)that an SET inverter logic circuit can withstand before its noise margin upper bound crosses the acceptable tolerance limit. It is found that SET inverter designed with CT : CG =0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, whichuses MCsimulator for SET devices alongwithconventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it has been demonstrated that the SET behavior under energy quantization can be predicted byslightlymodifyingthe existing SETcompact models that are valid for metallic devices having continuous energy states.