Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques. Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2. Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès. Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible. / Abstract : The single electron transistor (SET) is a nanoelectronic device very attractive due to its ultra-low power consumption and its high integration density, but he is not capable of completely replace CMOS technology. Nevertheless, the hybridization of these two technologies is an interesting approach since it combines the advantages of both technologies, in order to obtain circuits with new and unique functionalities. This thesis deals with the 3D monolithic integration of nanodevices in the back-end-ofline (BEOL) of a CMOS chip. This approach gives the opportunity to build hybrid circuits and to add value to CMOS chips without fundamentally changing the process fabrication of MOS transistors. This study is based on the nanodamascene process developed at UdeS, which is used to fabricate nanoelectronic devices on a SiO2 layer. This document presents the work done on the nanodamascene process optimization, in order to make it compatible with the BEOL of CMOS circuits. The development of plasma etching processes has been required to fabricate metallic and dielectric nanostructures useful to the fabrication of nanodevices. MIM junctions and metallic SET have been fabricated with the new reverse nanodamascene process on a SiO2 substrate. Electrical characterizations of MIM devices and SET formed with TiN/Al2O3 junctions have shown trap sites in the dielectric and a functional SET at low temperature (1.5 K). The transfer process on CMOS substrate and the vertical interconnection process have also been developed. Finally, a 3D circuit consisting of a titanium nanowire connected to a MOS transistor is fabricated and is functional. The results obtained during this thesis prove that the co-integration of nanoelectronic devices in the BEOL of a CMOS chip is possible, using a compatible process.

Although scalingof CMOS technology has been predicted to continue for another decade, novel technological solutions are required to overcome the fundamental limitations of the decananometer MOS transistors. Single Electron Transistor (SET) has attracted attention mainly because of its unique Coulomb blockade oscillations characteristics, ultra low power dissipation and nanoscale feature size. Despite the high potential, due to some intrinsic limitations (e.g., very low current drive) it will be very difficult for SET to compete head-to-head with CMOS’s large-scale infrastructure, proven design methodologies, and economic predictability. Nevertheless, the characteristics of SET and MOS transistors are quite complementary. SET advocates low-power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages like high-speed driving and voltage gain that can compensate the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single-electronics is unlikely in the near future, it is also true that combining SET and CMOS one can bring out new functionalities, which are unmirrored in pure CMOS technology. As the hybridization of CMOSand SET is gaining popularity, silicon SETs are appearing to be more promising than metallic SETs for their possible integration with CMOS. SETs are normally studied on the basis of the classical Orthodox Theory, where quantization of energy states in the island is completely ignored. Though this assumption greatly simplifies the physics involved, it is valid only when the SET is made of metallic island. As one cannot neglect the quantization of energy states in a semi conductive island, it is extremely important to study the effects of energy quantization on hybrid CMOSSET integrated circuits. The main objectives of this thesis are: (1) understand energy quantization effects on SET by numerical simulations; (2) develop simple analytical models that can capture the energy quantization effects; (3)analyze the effects of energy quantization on SET logic inverter, and finally; (4)developa CAD framework for CMOS-SETco-simulation and to study the effects of energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effects of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states.It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. Anew model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termedas “Quantization Threshold”)that an SET inverter logic circuit can withstand before its noise margin upper bound crosses the acceptable tolerance limit. It is found that SET inverter designed with CT : CG =0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, whichuses MCsimulator for SET devices alongwithconventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it has been demonstrated that the SET behavior under energy quantization can be predicted byslightlymodifyingthe existing SETcompact models that are valid for metallic devices having continuous energy states.

Cette étude porte sur l’intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d’économies d’énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d’intégration. Cette thèse se propose d’employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l’oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc. / This study deals with the hybrid integration of Single Electron Transistors (SET) on a CMOS technology node. SET devices present high potentiels, particularly in terms of energy efficiency, but can't completely replace CMOS in electrical circuits. However, SETs and CMOS devices combination can solve this issue, opening the way toward very low operating power circuits, and high integration density. This thesis proposes itself to use for Back-End-Of-Line (BEOL) SETs realization, meaning in the oxide encapsulating CMOS, the nanodamascene fabrication process devised by C. Dubuc.

Dans les années à venir, l’industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine ‘‘Beyond CMOS’’, ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. Ainsi, le caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d’envisager la réalisation de transistors et de cellules mémoires à haute densité d’intégration, basse consommation. L’objectif principal de ce travail de thèse est d’explorer et d’évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DGSETs dans une approche ‘‘cellules standards’’ ; et iii) l’exploration d’architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l’aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en terme de consommation d’énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiques. / In this work, we have presented a physics-based analytical SET model for hybrid SET-CMOS circuit simulations. A realistic SET modeling approach has been used to provide a compact SET model that takes several conduction mechanisms into account and closely matches experimental SET characteristics. The model is implemented in Verilog-A language, and can provide suitable environment to simulate hybrid SET-CMOS architectures. We have presented logic circuit design technique based on double gate metallic SET at room temperature. We have also shown the flexibility that the second gate can bring in order to configure the SET into P-type and N-type. Given that the same device is utilized, the circuit design approach exhibits regularity of the logic gate that simplifies the design process and leads to reduce the increasing process variations. Afterwards, we have addressed a new Boolean logic family based on DG-SET. An evaluation of the performance metrics have been carried out to quantify SET technology at the circuit level and compared to advanced CMOS technology nodes. SET-based static memory was achieved and performances metrics have been discussed. At the architectural level, we have investigated both full DG-SET based arithmetic logic blocks (FA and ALU) and programmable logic circuits to emphasize the low power aspect of the technology. The extra power reduction of SETs based logic gates compared to the CMOS makes this technology much attractive for ultra-low power embedded applications. In this way, architectures based on SETs may offer a new computational paradigm with low power consumption and low voltage operation. We have also addressed a flexible logic design methodology based on DG-SET transmission gates. Unlike conventional design approach, the XOR / XNOR behavior can be efficiently implemented with only 4 transistors. Moreover, this approach allows obtaining reconfigurable XOR / XNOR gates by swapping the cell biasing. Given that the same device is utilized, the structure can be physically implemented and established in a regular manner. Finally, complex logic gates based on DG-SET transmission gates offer an improvement in terms of transistor device count and power consumption compared to standard complementary SETs implementations.Process variations are introduced through our model enabling then a statistical study to better estimate the SET-based circuit performances and robustness. SET features low power but limited operating frequency, i.e. the parasitics linked to the interconnects reduce the circuit operating frequency as the SET Ion current is limited to the nA range. In term of perspectives: i) detailed studying the impact on SET-based logic cells of process variation and random back ground charge ii) considering multi-level computational model and their associate architectures iii) investigating new computation paradigms (neuro-inspired architectures, quantum cellular automata) should be considered for future works.