Nowadays, non-functional testing has a great impact on the real-time environment. Non-functional testing helps to analyze the performance of the application on both server and client. Load testing attempts to cause the system under test to respond incorrectly in a situation that differs from its normal operation, but rarely encountered in real world use. Examples include providing abnormal inputs to the software or placing real-time software under unexpectedly high loads. High loads are induced over the application to test the performance, but there is a possibility that particular pattern of the low load could also induce load on a real-time system. For example, repeatedly making a request to the system every 11 seconds might cause a fault if the system transitions to standby state after 10 seconds of inactivity. The primary aim of this study is to find out various low load input patterns affecting the software, rather than simply high load inputs. A quasi-experiment was chosen as a research method for this study. Performance testing was performed on the web application with the help of a tool called HP load runner. A comparison was made between low load and high load patterns to analyze the performance of the application and to identify bottlenecks under different load.

Majoriteten av idrottsskador inklusive skada på främre korsbandet (Anterior Cruciate Ligament, ACL) uppstår i slutet av träning/tävling när personen tenderar att vara trött. Nuvarande funktionstest inför återgång till idrott efter skada utvärderar ofta individens hoppförmåga i ett icke-uttröttat tillstånd. Syfte: Syftet med följande studie var att se huruvida prestationen i två olika enbenshopp kunde skilja sig mellan före och efter 25 minuters löpning, varav 15 minuter på hög-intensiv nivå och om hopprestationen skiljer sig mellan oskadade och ACL-opererade kvinnor. Metod: Totalt deltog 8 friska kvinnor, utan pågående besvär från nedre extremitet samt 6 färdigrehabiliterade ACL-opererade kvinnor som återgått till sin tidigare aktivitetsnivå. Deltagarna genomförde tester vid två olika tillfällen. Ett Pre-test-tillfälle då inträning av distans- och cross-overhopp samt ett max-pulstest (HRmax) på löpband utfördes. Ett Test-tillfälle där respektive hopp utfördes före och efter cirka 25 minuters löpning varav 15 minuter var på hög-intensiv nivå (>RPE 15 eller >85 % av HRmax). Total distans mättes, registrerades och analyserades för två godkända hopp per ben, tillstånd och hopptyp. Antal hopp-försök per ben och hopp registrerades. Ett symmetri index (LSI) beräknades för att bedöma om det förelåg en normal eller onormal sidoskillnad. Resultat: Cross-overhoppet var signifikant kortare efter löpning jämfört med före. Samma resultat syntes inte för distanshoppet. Ingen skillnad fanns mellan grupperna i hopplängd eller LSI-värden, före eller efter löpning. Ingen onormal sidoskillnad syntes före eller efter löpning i något utav hoppen. ACL-skadade behövde signifikant fler hoppförsök på det opererade benet i uttröttat tillstånd jämfört med det icke-opererade och jämfört med oskadade för att uppnå två godkända hopp. Slutsats: Cross-overhoppet försämrades av löpningen och kan därför sägas vara känsligt nog att kunna skilja uttröttat från icke-uttröttat tillstånd hos båda grupperna. Samma resultat syntes inte för distanshoppet. Det uttröttningsprotokoll och de hopptester som utfördes kunde inte frambringa några större förändringar eller olika sidoskillnader mellan färdigrehabiliterade ACL-opererade kvinnor som återgått till sin tidigare aktivitetsnivå och oskadade, generellt fysisk aktiva kvinnor. Viss osäkerhet kan ha funnits kvar hos det tidigare skadade benet eftersom fler hoppförsök krävdes i uttröttat tillstånd på det opererade benet jämfört med det icke-opererade benet eller jämfört med oskadade deltagare för båda hopptyperna. / Most sport injuries including anterior cruciate ligament-injury (ACL) occur at the end of sport events when the person tends to be fatigued. Despite this, the tests commonly used today to assess whether the individual should return to sports are performed in a non-fatigued state. Aim: The aim of this study was to compare effects of 25 minutes treadmill running, including 15 minutes at a level of high-intenisty on the performance of two different single-leg hop tests between un-injured women and women who underwent an ACL-reconstruction. Method: Eight un-injured women without any ongoing symptoms from either leg, and 6 women who had undergone an ACL-reconstruction, finished the rehabilitation program and returned to their pre-injury level of activity performed tests at two different occasions. The first occasion included technique training for each single-leg hop and a maximal heart rate test (HRmax) on a treadmill. On the second occasion subjects performed the single-leg hop for distance and the cross-over hop before and directly after 25 minutes running, including 15 minutes on a high-intensity level (>RPE 15 and/or >85 % HRmax). Total jump-distance was measured, registered and analysed for 2 approved trials per leg, condition and hop. A leg symmetry index (LSI) was calculated to assess side-to-side-differences. Results: The cross-over hop was significantly shorter after running in both groups, whereas no such effect was seen for the single-leg hop for distance. No difference was shown between groups in performed distance, side-to-side difference or LSI-values, before or after running any of the single-leg hops. Subjects in the ACL-group needed significantly more hop-trials on the operated leg compared to the non-operated leg and compared to un-injured subjects to achieve two qualified hops. Conclusions: Subjects jumped shorter in the cross-over hop after running. This hop can therefore be regarded as sensitive enough to tell fatigued state from a non-fatigued state in both groups. The fatigue protocol did not induce any side-to-side differences in subjects who had undergone ACL-reconstruction, finished their rehabilitation and returned to their pre-injury activity level. Some insecurity may still have been present in the previously injured leg since ACL-operated subjects needed more hop-trials for the operated leg compared to the non-operated leg or compared to un-injured subjects when fatigue.

Recent years have witnessed that standard telecommunication services evolved more and more to next generation value-added services. This fact is accompanied by a change of service characteristics as new services are designed to fulfil the customer’s demands instead of just focussing on technologies and protocols. These demands can be very specific and, therefore, diverse potential service functionalities have to be considered by the service providers. To make matters worse for service providers, a fast transition from concept to market product and low price of a new service is required due to the increasing competition in the telecommunication industry. Therefore, effective test solutions need to be developed that can be integrated in current value-added service development life-cycles. Besides, these solutions should support the involvement of all participating stakeholders such as the service provider, the test developers as well as the service developers, and, in order to consider an agile approach, also the service customer. This thesis proposes a novel framework for functional testing that is based on a new sort of description language for value-added services (Service Test Description). Based on instances of the Service Test Description, sets of reusable test components described by means of an applied Statecharts notation are automatically selected and composed to so-called behaviour models. From the behaviour models, abstract test cases can be automatically generated which are then transformed to TTCN-3 test cases and then assembled to an Executable Test Suite. Within a TTCN-3 test system, the Executable Test Suite can be executed against the corresponding value-added service referred to as System Under Test. One benefit of the proposed framework is its application within standard development life-cycles. Therefore, the thesis presents a methodology that considers both service development and test development as parallel tasks and foresees procedures to synchronise the tasks and to allow an agile approach with customer involvement. The novel framework is validated through a proof-of-concept working prototype. Example value-added services have been chosen to illustrate the whole process from compiling instances of the Service Test Description until the execution of automated tests. Overall, this thesis presents a novel solution for service providers to improve the quality of their provided value-added services through automated functional testing procedures. It enables the early involvement of the customers into the service development life-cycle and also helps test developers and service developers to collaborate.

I denna rapport presenteras hur en simulatorlösning för funktionstestning av en gruvmaskin har tagits fram. Arbetet har skett i Atlas Copcos regi och består av tre delar: kartläggning i form av intervjuer, utvärdering av befintliga simulatoralternativ och slutligen val och implementation av lösning.   Resultatet visar på en konceptuell prototyp, där en gruvmaskin visualiseras i en 3D-miljö tillsammans med en virtuell gruvgång. Detta möjliggör bland annat testning av autonom navigering, alltså att en gruvmaskin självständigt styr utifrån avläsning av tunnelväggar med hjälp av laser. Samtidigt tillåter lösningen också att kontrollvärden från olika sensorer, såsom vinkelgivare, kan hämtas ut ur simuleringen. / This report presents how a solution for functional testing of mine trucks involving a simulator has been developed. The project has been directed by Atlas Copco and consists of three parts: conduction of a survey in the form of interviews, evaluation of existing simulators and finally selection and implementation of a solution.   The result shows a mine truck visualized in a 3D environment with a virtual mining tunnel. This allows for testing of the autonomous navigation systems developed at Atlas Copco, where a machine uses readings from laser sensors to locate itself and navigate through mining tunnels without the help of an operator. At the same time, it allows relevant and interesting values from various sensors, such as inclinometers, to be extracted from the simulation environment.

This diploma thesis is focused on testing of Electronic Control Units, especially functional testing in which hardware and software is verified and also Model in the Loop, Software in the Loop, Processor in the Loop and Hardware in the Loop testing methods. Within practical part of this thesis testing stand for functional test of the ECU was developed and manufactured. It is connected to PC via Input/Output card, testing is controlled by MATLAB script. Whole process of testing is automated from initial upload of testing firmware to tested ECU over all phases of test up to bootloader flashing. Hardware in the Loop test was also created, in which ECU works as controller and DC motor is simulated in real time with PC in MATLAB environment.

Yes / The Stream X-Machine (SXM) testing method provides strong and repeatable guarantees of functional correctness, up to a specification. These qualities make the method attractive for software certification, especially in the domain of brokered cloud services, where arbitrage seeks to substitute functionally equivalent services from alternative providers. However, practical obstacles include: the difficulty in providing a correct specification, the translation of abstract paths into feasible concrete tests, and the large size of generated test suites. We describe a novel SXM verification and testing method, which automatically checks specifications for completeness and determinism, prior to generating complete test suites with full grounding information. Three optimisation steps achieve up to a ten-fold reduction in the size of the test suite, removing infeasible and redundant tests. The method is backed by a set of tools to validate and verify the SXM specification, generate technology-agnostic test suites and ground these in SOAP, REST or rich-client service implementations. The method was initially validated using seven specifications, three cloud platforms and five grounding strategies. / European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement no. 328392, the Broker@Cloud project [11].

O planejamento de experimentos em sistemas computacionais não é uma tarefa trivial, pois envolve diversas etapas tais como, o planejamento propriamente dito, a execução dos experimentos e a análise dos resultados. A definição e a utilização de metodologias adequadas para cada uma destas etapas facilita a obtenção dos resultados de um experimento em um sistema computacional. Neste trabalho são apresentados mecanismos para auxiliar o planejamento e execução de experimentos em sistemas orientados a serviços. O planejamento de experimento é realizado a partir de um modelo baseado nos conjuntos de entradas comuns a arquiteturas orientadas a serviço. A execução deste planejamento é feita em um ambiente colaborativo real, a qual auxilia a identificação de gargalos que não estão presentes em simulações ou modelos analíticos. Um estudo de caso aplicado na arquitetura WSARCH, possibilitou avaliar seu desempenho e identificar problemas de configuração / The design of experiments in computational systems is not a trivial task as it involves several steps such as planning and execution of the experiments and the analyse of the results. The use of appropriate methodologies for each of these steps makes it easier obtain the experiment results of a computer system. In this dissertation, mechanisms to assist the planning and execution of experiments in service-oriented systems are presented. The planning of the experiment is made according to a model based on a set of common entries for service-oriented architectures. The experiment execution is performed in a real collaborative environment, which helps to identify bottlenecks that are not found in simulations or analytical models. A study case applied in WSARCH architecture, enables to evaluate the performance and identify configuration problems

De nos jours, les mémoires embarquées sont les composants les plus denses dans les "System-On-Chips" (SOCs), représentant actuellement plus que 90% de leur superficie totale. Parmi les différents types de mémoires, les SRAMs sont très largement utilisées dans la conception des SOCs, particulièrement en raison de leur haute performance et haute densité d'intégration. En revanche, les SRAMs conçues en utilisant des technologies submicroniques sont devenus les principaux contributeurs de la consommation d'énergie globale des SOCs. Par conséquent, un effort élevé est actuellement consacré à la conception des SRAMs à faible consommation. En plus, en raison de leur structure dense, les SRAMs sont devenus de plus en plus susceptibles aux défauts physiques comparativement aux autres blocs du circuit, notamment dans les technologies les plus récentes. Par conséquent, les SRAMs se posent actuellement comme le principal détracteur du rendement des SOCs, ce qui cause la nécessité de développer des solutions de test efficaces ciblant ces dispositifs.Dans cette thèse, des simulations électriques ont été réalisées pour prédire les comportements fautifs causés par des défauts réalistes affectant les blocs de circuits spécifiques aux technologies SRAM faible consommation. Selon les comportements fautifs identifiés, différents tests fonctionnels, ainsi que des solutions de tests matériels, ont été proposés pour détecter les défauts étudiés. Par ailleurs, ce travail démontre que les circuits d'écriture et lecture, couramment incorporés dans les SRAMs faible consommation, peuvent être réutilisés pour augmenter le stress dans les SRAMs lors du test, ce qui permet d'améliorer la détection des défauts affectant la mémoire. / Nowadays, embedded memories are the densest components within System-On-Chips (SOCs), accounting for more than 90% of the overall SOC area. Among different types of memories, SRAMs are still widely used for realizing complex SOCs, especially because they allow high access performance, high density and fast integration in CMOS designs. On the other hand, high density SRAMs designed with deep-submicrometer technologies have become the main contributor to the overall SOC power consumption. Hence, there is an increasing need to design low-power SRAMs, which embed mechanisms to reduce their power consumption. Moreover, due to their dense structure, SRAMs are more are more prone to defects compared to other circuit blocks, especially in recent technologies. Hence, SRAMs are arising as the main SOC yield detractor, which raises the need to develop efficient test solutions targeting such devices.In this thesis, failure analysis based on electrical simulations has been exploited to predict faulty behaviors caused by realistic defects affecting circuit blocks that are specific to low-power SRAMs, such as power gating mechanisms and voltage regulation systems. Based on identified faulty behaviors, efficient March tests and low area overhead design for testability schemes have been proposed to detect studied defects. Moreover, the reuse of read and write assist circuits, which are commonly embedded in low-power SRAMs, has been evaluated as an alternative to increase stress in the SRAM during test phase and then improve the defect coverage.

Compte tenu de la complexité des circuits intégrés de nos jours et des nœuds technologiques qui ne cessent pas de diminuer, être au rendez-vous avec les demandes de design, test et fabrication des dispositifs de haute qualité est devenu un des plus grands défis. Avoir des circuits intégrés de plus en plus performants devrait être atteint tout en respectant les contraintes de basse consommation, de niveaux de fiabilité demandés, de taux de défauts acceptables ainsi que du bas coût. Avec ce fascinant progrès de l’industrie des semi-conducteurs, les processus de fabrication sont devenus de plus en plus difficile à contrôler, ce qui rend les puces électroniques de nos jours plus disposés aux défauts physiques. Le test était et restera l’unique solution pour lutter contre l’occurrence des défauts de fabrication ; même il est devenu un facteur prédominant dans le coût totale de fabrication des circuits intégrés. Même si des solutions de test, qui existent déjà, étaient capables de satisfaire ce fameux compromis coût-qualité ces dernières années, il arrive d’observer encore des mécanismes de défauts malheureusement incontrôlables. Certains sont intrinsèquement reliés au processus de fabrication en lui-même. D’autres reviennent sans doute aux pratiques de test et surtout quand on analyse le taux de défauts détectés et le niveau de fiabilité atteint.L’objectif principal de cette thèse est d’implémenter des stratégies de test robustes et efficaces qui répondent aux lacunes des techniques de tests classiques et qui proposent des modèles de fautes plus réalistes et répondent au mieux aux attentes des fournisseurs. Dans l’objectif d’améliorer l’efficacité de test en termes de coût, capacité de couverture de faute, nous présentons divers contributions significatives qui touchent différents domaines entre-autres le test sur le terrain, les tests à hautes fréquences sous contraintes de puissance et finalement le test des chaines de scan.La partie majeure de cette thèse était consacrée pour le développement de nouvelles techniques de tests fonctionnels ciblant les systèmes à processeurs.Les méthodologies appliquées couvrent les problèmes de test sur terrain aussi bien que les problèmes de test de fabrication. Dans le premier cas, la techniques adoptée consiste à fusionner et compacter un ensemble initial de programmes fonctionnels afin d’atteindre une couverture de faute satisfaisante tout en respectant les contraintes du test sur terrain (temps de test réduit et ressource mémoire limitée). Cependant dans le deuxième cas, comme nous avons assez d’informations sur la structure du design, nous proposons un nouveau protocole de test qui va exploiter l’architecture de test existante. Dans ce contexte, nous avons validé et confirmé la relation complémentaire qui joint le test fonctionnel avec le test structurel. D’autres part, cette prometteuse approche assure un test qui respecte les limites de la consommation fonctionnelle et donc une fiabilité meilleure.La dernière contribution de cette thèse accorde toute l’attention à l’amélioration de test de la structure DFT « Design For Test » la plus utilisée qui est la chaîne de scan. Nous présentons dans cette contribution une approche de test qui cible les défauts physiques au sein de la cellule en elle-même.Cette approche représente une couverture de défauts meilleure et une longueur de test plus réduit si nous la comparons avec l’ATPG classique ciblant les mêmes défauts « Intra-cell defect ATPG ».Comme résultat majeur de cette efficace solution de test, nous avons observé une amélioration de 7.22% de couverture de défaut accompagné d’une réduction de 33.5% du temps de test en comparaison avec la couverture et le temps du test atteints par le « Cell-awer ATPG ». / In light of the aggressive scaling and increasing complexity of digital circuits, meeting the demands for designing, testing and fabricating high quality devices is extremely challenging.Higher performance of integrated circuits needs to be achieved while respecting the constraints of low power consumption, required reliability levels, acceptable defect rates and low cost. With these advances in the SC industry, the manufacturing process are becoming more and more difficult to control, making chips more prone to defects.Test was and still is the unique solution to cover manufacturing defects; it is becoming a dominant factor in overall manufacturing cost.Even if existing test solutions were able to satisfy the cost-reliability trade-off in the last decade, there are still uncontrolled failure mechanisms. Some of them are intrinsically related to the manufacturing process and some others belong to the test practices especially when we consider the amount of detected defects and achieved reliability.The main goal of this thesis is to implement robust and effective test strategies to complement the existing test techniques and cope with the issues of test practices and fault models. With the objective to further improve the test efficiency in terms of cost and fault coverage capability, we present significant contributions in the diverse areas of in-field test, power-aware at-speed test and finally scan-chain testing.A big part of this thesis was devoted to develop new functional test techniques for processor-based systems. The applied methodologies cover both in-field and end-of manufacturing test issues. In the farmer, the implemented test technique is based on merging and compacting an initial functional program set in order to achieve higher fault coverage while reducing the test time and the memory occupation. However in the latter, since we already have the structure information of the design, we propose to develop a new test scheme by exploiting the existing scan chain. In this case we validate the complementary relationship between functional and structural testing while avoiding over as well under-testing issues.The last contribution of this thesis deals with the test improvement of the most used DFT structure that is the scan chain. We present in this contribution an intra-cell aware testing approach showing higher intra-cell defect coverage and lower test length when compared to conventional cell-aware ATPG. As major results of this effective test solution, we show that an intra-cell defect coverage increase of up to 7.22% and test time decrease of up to 33.5 % can be achieved in comparison with cell-aware ATPG.

O planejamento de experimentos em sistemas computacionais não é uma tarefa trivial, pois envolve diversas etapas tais como, o planejamento propriamente dito, a execução dos experimentos e a análise dos resultados. A definição e a utilização de metodologias adequadas para cada uma destas etapas facilita a obtenção dos resultados de um experimento em um sistema computacional. Neste trabalho são apresentados mecanismos para auxiliar o planejamento e execução de experimentos em sistemas orientados a serviços. O planejamento de experimento é realizado a partir de um modelo baseado nos conjuntos de entradas comuns a arquiteturas orientadas a serviço. A execução deste planejamento é feita em um ambiente colaborativo real, a qual auxilia a identificação de gargalos que não estão presentes em simulações ou modelos analíticos. Um estudo de caso aplicado na arquitetura WSARCH, possibilitou avaliar seu desempenho e identificar problemas de configuração / The design of experiments in computational systems is not a trivial task as it involves several steps such as planning and execution of the experiments and the analyse of the results. The use of appropriate methodologies for each of these steps makes it easier obtain the experiment results of a computer system. In this dissertation, mechanisms to assist the planning and execution of experiments in service-oriented systems are presented. The planning of the experiment is made according to a model based on a set of common entries for service-oriented architectures. The experiment execution is performed in a real collaborative environment, which helps to identify bottlenecks that are not found in simulations or analytical models. A study case applied in WSARCH architecture, enables to evaluate the performance and identify configuration problems