published_or_final_version / Computer Science and Information Systems / Master / Master of Philosophy

During the past two decades, techniques and devices were developed to transmit and receive signals with a phased array instead of a single coil in the MRI (Magnetic Resonance Imaging) system. The two techniques to simultaneously transmit and receive RF signals using phased arrays are called parallel excitation (pTx) and parallel imaging (PI), respectively. These two techniques lead to shorter transmit pulses for higher imaging quality and faster data acquisition correspondingly. This dissertation focuses on improving the efficiency of the pTx pulse design and the PI reconstruction in MRI. Both PI and pTx benefit from the increased number of elements of the array. However, efficiency concerns may arise which include: (1) In PI, the computation cost of the reconstructions and the achievable acceleration factors and (2) in pTx, the pulse design speed and memory cost. The work presented in this dissertation addresses these issues. First, a correlation based channel reduction algorithm is developed to reduce the computation cost of PI reconstruction. In conventional k-domain methods, the individual channel data is reconstructed via linear interpolation of the neighbourhood data from all channels. In this proposed algorithm, we choose only a subset of the channels based on the spatial correlation. The results have shown that the computation cost can be significantly reduced with similar or higher reconstruction accuracy. Then, a new parallel imaging method named parallel imaging using localized receive arrays with Sinc interpolation(PILARS) is proposed to improve the actual acceleration factor and to reduce the computation cost. It employs the local support of individual coils and pre-determines the magnitude of the reconstruction coefficients. Thus, it requires much less auto-calibration signals (ACS) data and achieves higher acceleration factors. The results show that this method can increase the acceleration factor and the reconstruction speed while achieving the same level of reconstruction quality. Finally, a fast pTx pulse design method is proposed to accelerate the design speed. This method is based on the spatial domain pulse design method and can be used to accelerate similar methods. We substitute the two computational expensive matrix- vector multiplications in the conjugate gradient (CG) solver with gridding and fast Fourier transform (FFT). Theoretical and simulation results have shown that the design speed can be improved by 10 times. Meanwhile, the memory cost is reduced by 103 times. This breaks the memory burden of implementing pulse designs on GPU which enables further accelerations.

Power electronics are becoming established in ever broadening areas of industry. The transition from previous generation technology is driven by the oportunity for improvements in controllability, efficiency, and longevity. A wide variety of power semiconductors are available, however power handling capacity is still a significant limitation for many applications. An increase in the capacity of a single device is usually accompanied by a drop in switching frequency, and hence achievable system bandwidth. Increased capacity can be attained without this loss in bandwidth by using multiple lower power devices in parallel. Products based on parallel device topologies are already present in the marketplace, however there are many associated complications. The nature of these complications depends on the control method and topology used, but no system combines high performance and high power with high reliability and easy maintainability. This research aims to identify and develop a method that would provide a system of voltage source inverters with a total capacity in excess of 10MVA, with effective control bandwidth comparable to a 100kVA system. Additionally, the method should be equally applicable at still higher power levels in the future with the anticipated development of higher capacity power semiconductors. The primary goal when using paralleled devices is to achieve an even distribution of system load between them, as unbalanced load leads to poor system utilisation. Devices can be paralleled either passively, in which devices are controlled in common and characteristics inherent to the device are relied upon to balance load; or actively, in which devices are individually controlled and monitored to improve load balance. A key component of the thesis is the identification and analysis of the inadequacies inherent to passively paralleled systems. It is the limitations of passive paralleling that provide the motivation to develop an active parallel control mechanism. Following the analysis, an active control algorithm is developed and implemented on a paralleled system. The proposed system topology consists of an array of medium power Voltage Source Inverter (VSI) modules operating in parallel. Each module is controlled semi-independently at a local level, with an inter-module communications network to enable active equalisation of module load, and redundant fault management. An innovative load equalisatiion algorithm is developed and proven, the key feature of which is this inclusion of a synthetic differential resistance between modules within the system. The result is a modular expandable structure offering the potential for very high power capacity combined with quality of response usually only found in low power systems. The system as a whole is extremely reliable as any module can be isolated in the event of a fault without significantly affecting the remainder of the network. Performance results from both simulation and experimentation on a two module small scale prototype are given. Using the developed topology and control method extremely accurate load balancing can be achieved without degradation of the response characteristics. The system is tested up to only 2.4kW in the course of this research, but the correlation with simulation is high and gives confidence that the developed mechanism will allow the 10MV A goal to be achieved. Following the developmental stage of this research the technology has been applied to a commercial system comprising parallel structures of up to 8 modules with a total power handling capacity of 1MVA with no deterioration in performance. 2MVA systems are deliverable with the current technology without any changes, and higher power levels are expected to be easily achieved.

In recent years, powerful theoretical techniques have been developed for supporting communication, synchronization and fault tolerance in general purpose parallel computing. The proposition of this thesis is that different techniques should be used to support different algorithms. The determining factor is granularity, or the extent to which an algorithm uses long blocks for communication between processors. We consider the Block PRAM model of Aggarwal, Chandra and Snir, a synchronous model of parallel computation in which the processors commu- nicate by accessing a shared memory. In the Block PRAM model, there is a time cost for each access by a processor to a block of locations in the shared memory. This feature of the model encourages the use of long blocks for communication. In the thesis we present Block PRAM algorithms and lower bounds for specific problems on arrays, lists, expression trees, graphs, strings, binary trees and butterflies. These results introduce useful basic techniques for parallel computation in practice, and provide a classification of problems and algorithms according to their granularity. Also presented are optimal algorithms for universal hashing and skewing, which are techniques for sup- porting conflict-free memory access in general- and special-purpose parallel computations, respectively. We explore the Block PRAM model as a theoretical basis for the design of scalable general purpose parallel computers. Several simulation results are presented which show the Block PRAM model to be comparable to, and competitive with, other models that have been proposed for this role. Two major advantages of machines based on the Block PRAM model is that they are able to preserve the granularity properties of individual algorithms and can efficiently incorporate a significant degree of fault tolerance. The thesis also discusses methods for the design of algorithms that do not use synchronization. We apply these methods to define fast circuits for several fundamental Boolean functions.

Thesis (MAppSc) -- University of South Australia, 1993

Thesis (M.S.)--Wake Forest University. Dept. of Computer Science, 2007. / Vita. Includes bibliographical references (leaves 69-71)

Thesis (M.S.)--Villanova University, 2008. / Computer Science Dept. Includes bibliographical references.

Thesis (M.C.S.) - Carleton University, 2005. / Includes bibliographical references (p. 119-124). Also available in electronic format on the Internet.

Thesis (M.S.)--University of Texas at El Paso, 2008. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.

Thesis (Ph. D.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 127-138). Also available via the Internet.