With the availability of fast microprocessors and small-scale multiprocessors, internode communication has become an increasingly important factor that limits the performance of parallel computers. Essentially, message-passing parallel computers require extremely short communication latency such that message transmissions have minimal impact on the overall computation time. This thesis concentrates on issues regarding hardware communication latency in single-hop reconfigurable networks, and software communication latency regardless of the type of network. The first contribution of this thesis is the design and evaluation of two different categories of prediction techniques for message-passing systems. This thesis utilizes the communications locality property of message-passing parallel applications to devise a number of heuristics that can be used to predict the target of subsequent communication requests, and to predict the next consumable message at the receiving ends of communications. Specifically, I propose two sets of predictors: Cycle-based predictors, which are purely dynamic predictors, and Tag-based predictors, which are static/dynamic predictors. The performance of the proposed predictors, specially Better-cycle2 and Tag-bettercycle2, are very well on the application benchmarks studied in this thesis. The proposed predictors could be easily implemented on the network interface due to their simple algorithms and low memory requirements. As the second contribution of this thesis, I show that majority of reconfiguration delays in single-hop reconfigurable networks can be hidden by using one of the proposed high hit ratio predictors. The proposed predictors can be used in establishing a communication pathway between a source and a destination in such networks before this pathway is to be used. This thesis' third contribution is the analysis of a broadcasting algorithm that utilizes latency hiding and reconfiguration in the network to speed the broadcasting operation. The analysis brings up closed formulations that yields the termination time of the algorithms. The thesis' fourth contribution is a new total exchange algorithm in single-hop reconfigurable networks. I conjecture that this algorithm ensures a better termination time than what can be achieved by either of the direct, and standard exchange algorithms. The fifth contribution of this thesis is the use and evaluation of the proposed predictors to predict the next consumable message at the receiving ends of communications. This thesis contributes by claiming that these message predictors can be efficiently used to drain the network and cache the incoming messages even if the corresponding receive calls have not been posted yet. This way, there is no need to copy the early arriving messages into a temporary buffer. The performance of the proposed predictors, Single-cycle, Tag-cycle2 and Tag-bettercycle2, on the parallel applications are quite promising and suggest that prediction has the potential to eliminate most of the remaining message copies. / Graduate

Depending on the scale of the problem, continuous system simulation is usually carried out on large computer systems or in personal computers running continuous system simulation languages; there is little in between. This thesis describes the development of an inexpensive parallel-processing simulator in which outwardly identical processing elements are configured to digitally simulate continuous system transfer functions and the other components needed to model the computing and control functions of physical systems.

No description available.

In order to utilize parallel computers, four approaches, broadly speaking, to the provision of parallel software have been followed: (1) automatic production of parallel code by parallelizing—compilers which act on sequential programs written in existing languages; (2) "add on" features to existing languages that enable the programmer to make use of the parallel computer—these are specific to each machine; (3) full-blown parallel languages—these could be completely new languages, but usually they are derived from existing languages; (4) the provision of tools to aid the programmer in the detection of inherent parallelism in a given algorithm and in the design and implementation of parallel programs.

The present Thesis addresses the problem of specification and verification of communicating systems with value passing. We assume that such systems are described in the well-known Calculus of Communicating Systems, or rather, in its value passing version. As a specification language we propose an extension of the Modal μ-Calculus, a poly-modal first-order logic with recursion. For this logic we develop a proof system for verifying judgements of the form b ⊢ Ε : Φ where E is a sequential CCS term and b is a Boolean assumption about the value variables occurring free in E and Φ. Proofs conducted in this proof system follow the structure of the process term and the formula. This syntactic approach makes proofs easier to comprehend and machine assist. To avoid the introduction of global proof rules we adopt a technique of tagging fixpoint formulae with all relevant information needed for the discharge of reoccurring sequents. We provide such tagged formulae with a suitable semantics. The resulting proof system is shown to be sound in general and complete (relative to external reasoning about values) for a large class of sequential processes and logic formulae. We explore the idea of using tags to three different settings: value passing, extended sequents. and negative tagging. / Graduate

Commercial applications, including Blockchain, require large numbers of cryptographic signing and verification operations, increasingly using Elliptic Curve Cryptography. This uses a group operation (called point addition) in the set of points on an elliptic curve over a prime field. Scalar multiplication of the repeated addition of a fixed point, P , in the curve. Along with the infinity point, which serves as the identity of addition and the zero of scalar multiplication, this forms a vector space over the prime field. The scalar multiplication can be accelerated by decomposing the number of additions into nibbles or other digits, and using a pre-computed table of values P , 2P , 3P, . . . This is called a windowed method. To avoid side-channel attacks, implementations must ensure that the time and power used do not depend on the scalar. Avoiding conditional execution ensures constant-time and constant-power execution. This thesis presents a theoretical reduction in latency for the windowed method by introducing parallelism. Using three cores can achieve an improvement of 42% in the latency versus a single-threaded computation. / Thesis / Master of Science (MSc)

An examination of the lives of Baudelaire and Huysmam, showing how they both passed through the three stages of Dandy, Decadent and Satanist on the way to a final Spirituality. / Thesis / Master of Arts (MA)

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No description available.

No description available.