Thesis (Ph. D.)--University of Hong Kong, 2007. / Title proper from title frame. Also available in printed format.

Thesis (M.S.)--State University of New York at Binghamton, Electrical and Computer Engineering Dept., 2006. / Includes bibliographical references.

The microprocessors will have more than a billion logic transistors on a single chip in the near future. Several alternatives have been suggested for obtaining highest performance with billion-transistor chips. To achieve the highest performance possible, an on-chip multiprocessor will become one promising alternative to the current superscalar microprocessor. It may execute multiple threads effectively on multiple processors in parallel if the application program is parallelized properly. This increases the utilization of the processor and provides latency tolerance for the latency caused from data dependency and cache misses. The Electronics and Telecommunications Research Institute (ETRI) in South Korea developed an on-chip multiprocessor RAPTOR Simulator "RapSim", which contains four SPARC microprocessor cores in it. To support this 4-way multiprocessor simulator, Multithreaded Mini Operating System (MMOS) was developed by OSU MMOS group. RapSim runs multiple threads on multiple processor cores concurrently. POSIX threads was used to build Symmetric Multiprocessor (SMP) safe Pthreads package, called MMOS. Benchmarks should be properly parallelized by the programmer to run multiple threads across the multiple processors simultaneously. Performance simulation results shows the RAPTOR can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multiprocessor designs. / Graduation date: 2000

There appears to be a broad agreement that high-performance computers of the future will be Massively Parallel Architectures (MPAs), where all processors are interconnected by a high-speed network. One of the major problems with MPAs is the latency observed for remote operations. One technique to hide this latency is multithreading. In multithreading, whenever an instruction accesses a remote location, the processor switches to the next available thread waiting for execution. There have been a number of architectures proposed to implement multithreading. One such architecture is the Threaded Abstract Machine (TAM). It supports fine-grain multithreading by an appropriate compilation strategy rather that through elaborate hardware. Experiments on TAM have already shown that fine-grain multithreading on conventional architectures can achieve reasonable performance. However, a significant deficiency of the conventional design in the context of fine-grain program execution is that the message handling is viewed as an appendix rather than as an integral, essential part of the architecture. Considering that message handling in TAM can constitute as much as one fifth to one half of total instructions executed, special effort must be given to support it in the underlying hardware. This thesis presents the design modifications required to efficiently support message handling for fine-grain parallelism on stock processors. The idea of having a separate processor is proposed and extended to reduce the overhead due to messages. A detailed hardware is designed to establish the interface between the conventional processor and the message-handling processor. At the same time, the necessary cycle cost required to guarantee atomicity between the two processors is minimized. However, the hardware modifications are kept to a minimum so as not to disturb the original functionality of a conventional RISC processor. Finally, the effectiveness of the proposed architecture is analyzed in terms of its impact on the system. The distribution of the workload between both processors is estimated to indicate the potential speed-up that can be achieved with a separate processor to handle messages. / Graduation date: 1995

Many search problems are commonly solved with combinatoric algorithms that unnecessarily duplicate and serialize work at considerable computational expense. There are techniques available that can eliminate redundant computations and perform remaining operations concurrently, effectively reducing the branching factors of these algorithms. This thesis applies these techniques to the problem of parsing natural language. The result is an efficient programming language that can reduce some of the expense associated with principle-based parsing and other search problems. The language is used to implement various natural language parsers, and the improvements are compared to those that result from implementing more deterministic theories of language processing.

This thesis presents an evolutionarily design change for the Delta parallel robot. The proposed design change increases the useful workspace of the robot and aids in permanently avoiding singularities in the workspace. This is accomplished by means of a new intermediate link parallel to the 4 bar linkage. The addition of the new link simultaneously increases the total workspace volume and decreases the dexterity without significantly affecting the stiffness. The design is analyzed and the inverse kinematics, Jacobian, sti ness and dexterity relations are formulated. The relations are then converted into a form that is usable by MATLAB to calculate di erent workspaces that illustrate the advantages of the new design. Subsequently, an optimization problem is formulated that aims to take advantage of the new attributes to create a balanced robot that further illustrates the benefits of the new design. The results are clearly illustrated by comparing plotted sections of workspace from both the optimized and unoptimized workspace. Lastly, the design is developed into a 3D model which is then fabricated into a working prototype to test and verify functionality. / UOIT

During the design phase of modern digital and mixed signal devices, simulations are run to determine the fitness of the proposed design. Some of these simulations can take large amounts of time, thus slowing down the time to manufacture of the system prototype. One of the typical simulations that is done is an integration simulation that simulates the hardware and software at the same time. Most simulators used in this task are monolithic simulators. Some simulators do have the ability to have external libraries and simulators interface with it, but the setup can be a tedious task. This thesis proposes, implements and evaluates a distributed simulator called PDQScS, that allows for speed up of the simulation to reduce this bottleneck in the design cycle without the tedious separation and linking by the user. Using multiple processes and SMP machines a simulation run time reduction was found.

This thesis describes techniques for defining independent tasks in Java programs forparallelization. Existing Java parallelization APIs like JOMP, Parallel Java,Deterministic Parallel Java, JConqurr and JaMP are discussed. We have seen that JaMPis an implementation of OpenMP for Java, and it has a set of OpenMP directives andruntime library functions. We have discussed that JaMP has source to byte codecompiler, and it does not help in debugging the parallel source codes. There is no designtime syntax checking support of JaMP directives, and we know about mistakes onlywhen we compile the source code with JaMP compiler. So we have decided tocontribute JaMP with adding an option in the compiler to get parallel source code. Wehave created an eclipse plug-in to support design time syntax checking of JaMPdirectives too. It also helps the programmers to get quickly parallel source code withjust one click instead of using shell commands with JaMP compiler.

Industrial robots and automation technology have advanced rapidly in the last several decades. New types of manipulators that uses parallel mechanisms are becoming more popular due to their high speed and high stiffness. This thesis focuses on a sub-class of parallel manipulators that uses cables to replace rigid links for further increase in speed. The design strategies in this study were expanded from research works by Khajepour. Behzadipour, and Edmon Chan. This thesis presents analysis and development of a new cable-based planar parallel manipulator that is based on a previous prototype built by Edmon Chan. The new manipulator design added a new rotational DOF to the end-effector, and the number of cables are doubled in order to increase the stiffness. New methods for kinematics and dynamics analysis are formulated to make the procedure more systematic. A new mathematical formulation for stiffness matrix of the end-effector is presented. The resultant stiffness matrix is equivalent to the stiffness matrix formulated by Behzadipour. Additional stiffness analysis is conducted on valid range of stiffness calculation and comparison of different cable configurations. A multi-objective optimization problem is formulated in order to search for the best set of design parameters for the manipulator, and it is solved with an exhaustive complete search method. A physical prototype of the manipulator is modelled and manufactured with the help of partners from Conestoga college. Experiments with the manipulator show that more powerful motors are needed to run the robot at full speed. Motor torque measurements show that the dynamics analysis of the manipulator is valid. Stiffness of the manipulator is measured by applying external force to the end-effector, and it is shown to be strong. The manipulator is able to demonstrate a sort and pick-and-place operation at 60 cycles per minute while running at 70% of the maximum speed, with an acceleration of 2.8 g and velocity of 4 m/s.

During the design phase of modern digital and mixed signal devices, simulations are run to determine the fitness of the proposed design. Some of these simulations can take large amounts of time, thus slowing down the time to manufacture of the system prototype. One of the typical simulations that is done is an integration simulation that simulates the hardware and software at the same time. Most simulators used in this task are monolithic simulators. Some simulators do have the ability to have external libraries and simulators interface with it, but the setup can be a tedious task. This thesis proposes, implements and evaluates a distributed simulator called PDQScS, that allows for speed up of the simulation to reduce this bottleneck in the design cycle without the tedious separation and linking by the user. Using multiple processes and SMP machines a simulation run time reduction was found.