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Synthesis techniques for regular arrays provide a disciplined and well-founded approach to the design of classes of parallel algorithms. The design process is guided by a methodology which is based upon a formal notation and transformations. The mathematical model underlying synthesis techniques is that of affine Euclidean geometry with embedded lattice spaces. Because of this model, computationally powerful methods are provided as an effective way of engineering regular arrays. However, at present the applicability of such methods is limited to so-called affine problems. The work presented in this thesis aims at widening the applicability of standard synthesis methods to more general classes of problems. The major contributions of this thesis are the characterisation of classes of integral and dynamic problems, and the provision of techniques for their systematic treatment within the framework of established synthesis methods. The basic idea is the transformation of the initial algorithm specification into a specification with data dependencies of increased regularity, so that corresponding regular arrays can be obtained by a direct application of the standard mapping techniques. We will complement the formal development of the techniques with the illustration of a number of case studies from the literature.

This thesis is devoted to the construction and analysis of models which can be used to evaluate the performance and reliability of distributed systems. The general object of the research therefore is to extend the types of queueing models with breakdowns which have been solved, with a particular interest in networking structures. The systems that are studied involve various collections of servers and their associated queues. These range from isolated nodes, though parallel nodes coupled by the effect of breakdowns on arrivals, to pipelines of such parallel stages and more general networks. The issues that are explored include the influence of breakdowns and repairs on delays, job losses and optimal routeing. Obtaining performance measures for interacting queues is difficult, however a degree of abstraction has been used here which allows long run averages to be calculated (exactly in many cases) for quite complex systems. A variety of different techniques are used in order to obtain solutions to these models, including exact equations, exact numerical and approximate numerical techniques.

Industrial robots and automation technology have advanced rapidly in the last several decades. New types of manipulators that uses parallel mechanisms are becoming more popular due to their high speed and high stiffness. This thesis focuses on a sub-class of parallel manipulators that uses cables to replace rigid links for further increase in speed. The design strategies in this study were expanded from research works by Khajepour. Behzadipour, and Edmon Chan. This thesis presents analysis and development of a new cable-based planar parallel manipulator that is based on a previous prototype built by Edmon Chan. The new manipulator design added a new rotational DOF to the end-effector, and the number of cables are doubled in order to increase the stiffness. New methods for kinematics and dynamics analysis are formulated to make the procedure more systematic. A new mathematical formulation for stiffness matrix of the end-effector is presented. The resultant stiffness matrix is equivalent to the stiffness matrix formulated by Behzadipour. Additional stiffness analysis is conducted on valid range of stiffness calculation and comparison of different cable configurations. A multi-objective optimization problem is formulated in order to search for the best set of design parameters for the manipulator, and it is solved with an exhaustive complete search method. A physical prototype of the manipulator is modelled and manufactured with the help of partners from Conestoga college. Experiments with the manipulator show that more powerful motors are needed to run the robot at full speed. Motor torque measurements show that the dynamics analysis of the manipulator is valid. Stiffness of the manipulator is measured by applying external force to the end-effector, and it is shown to be strong. The manipulator is able to demonstrate a sort and pick-and-place operation at 60 cycles per minute while running at 70% of the maximum speed, with an acceleration of 2.8 g and velocity of 4 m/s.

Frequency scaling in traditional computing systems has hit the power wall and multicore computing is here to stay. Unlike homogeneous multicores which have uniform architecture and instruction set across cores, heterogenous multicores have differentially capable cores to provide optimal performance for specialized functionality. However, this heterogeneity also translates into difficult programming models, and extracting its potential is not trivial. The Cell Broadband Engine by the Sony Toshiba IBM(STI) consortium was amongst the first heterogenous multicore systems with a single Power Processing Unit(PPU) and 8 Synergistic Processor Units (SPUs). We address the issue of porting an existing sequential C/C++ codebase on to the Cell BE through compiler driven program analysis and profiling. Until parallel programming models evolve, the "interim" solution to performance involves speeding up legacy code by offloading computationally intense parts of a sequential thread to the co-processor; thus using it as an accelerator. Unique architectural characteristics of an accelerator makes this problem quite challenging. On the Cell, these characteristics include limited local store of the SPU, high latency of data transfer between PPU and SPU, lack of branch prediction unit, limited SIMDizability, expensive scalar code etc. In particular, the designers of the Cell have opted for software controlled memory on its SPUs to reduce power consumption and to give programmers more control over the predictability of latency. The lack of a hardware cache on the SPU can create performance bottlenecks because any data that needs to be brought in to the SPU must be brought in using a DMA call. The need for supporting a software controlled cache is thus evident for irregular memory accesses on the SPU. For such a cache to result in improved performance, the amount of time spent in book-keeping and tracking at run-time should be minimal. Traditional algorithms like LRU, when implemented in software incur overheads on every cache hit because appropriate data structures need to be updated. Such overheads are on off critical path for traditional hardware cache but on the critical path for a software controlled cache. Thus there is a need for better management of "data movement" for the code that is offloaded on to the SPU. This thesis addresses the "code partitioning" problem as well as the "data movement" problem. We present GLIMPSES - a compiler driven profiling tool that analyzes existing C/C++ code for its suitability for porting to the Cell, and presents its results in an interactive visualizer. Software Controlled Cache - an improved eviction policy that exploits information gleaned from memory traces generated through offline profiling. The trace is analyzed to provide guidance for a run-time state machine within the cache manager; resulting in reduced run-time overhead and better performance. The design tradeoffs and several pros and cons of this approach are brought forth as well. It is shown that with just about the right amount of runtime book-keeping and decision making, one can get to the difficult solution space of the right balance to achieve high performance.

With the proliferation of parallel computing, parallel computer-aided design (CAD) has received significant research interests. Transient transistor-level circuit simulation plays an important role in digital/analog circuit design and verification. Increased VLSI design complexity has made circuit simulation an ever growing bottleneck, making parallel processing an appealing solution for addressing this challenge. In this thesis, we propose and develop a parallel and distributed multi-algorithm approach to leverage the power of multi-core computer clusters for speeding up transistor-level circuit simulation. The targeted multi-algorithm approach provides a natural paradigm for exploiting parallelism for circuit simulation. Parallel circuit simulation is facilitated through the exploration of algorithm diversity where multiple simulation algorithms collaboratively work on a single simulation task. To utilize computer clusters comprising of multi-core processors, each algorithm is executed on a separate node with sufficient system resource such as processing power, memory and I/O bandwidth. We propose two communication schemes, namely master-slave and peer-to-peer schemes, to allow for inter-algorithm communication. Compared with the shared-memory based multi-algorithm implementation, the proposed simulation approach alleviates cache/memory contention as a result of multi-algorithm execution and provides further runtime speedups.

Thesis (Ph.D.)--McMaster University, 2005. / Supervisor: M. A. Elbestawi. Includes bibliographical references (leaves 183-204).

Thesis (M.S.)--Ohio University, November, 1986. / Title from PDF t.p.

Thesis (Ph.D.) -- University of Adelaide, Dept. of Computer Science, 1999. / Bibliography: leaves 231-246.