The development of single-chip transmitters and receivers is hindered by several obstacles. The main difficulties include the low quality factor of MMIC filters, limited output power of solid state devices at millimeter-wave frequencies, and poor frequency stability of monolithic oscillators. This research investigates novel techniques to overcome these challenges. The scope of work includes proposal of new circuit structures and techniques, theoretical analyses, MMIC realisations and experimental verifications with measured results. To reduce filtering requirements, single-ended and single-balanced resistive mixers, utilising a unique resonance technique to achieve port isolations, are developed for V-band direct conversion receivers. A double-balanced resistive mixer, with high input power capability to reduce output power amplification requirements is also developed for millimeter-wave transmitters. A distributed resistive mixer is proposed to achieve wideband performance with low intermodulation. As an alternative to the use of baluns for generating anti-phase signals required in balanced mixers, a balanced oscillator is introduced. This novel oscillator can also operate as a power combining oscillator to obtain higher output power. In addition, a transmission-line stabilising technique can be applied to improve the oscillator phase noise. For the analysis of mixer circuits, the large-signal / small-signal analysis technique is extended to the case of multiple device mixers. For baluns used in the balanced mixers, a simplified analysis is applied, leading to a new class of impedance transforming baluns, which can be matched at all ports. The MMIC mixers, oscillator and baluns are realised using Marconi Caswell Ltd. foundry process. The performances of the fabricated MMICs are verified using on-wafer measurements. Theoretical analyses of the multiple device mixers and baluns are in good agreement with experimental results. The oscillator power combining and frequency stabilising techniques are also demonstrated experimentally.

Submitted by Nayara Passos (nayara.passos@ufpe.br) on 2015-03-13T12:04:17Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) TESE Max Santana Rolemberg Farias.pdf: 3331146 bytes, checksum: aafe22682c1e4d4144f19615252785b9 (MD5) / Approved for entry into archive by Daniella Sodre (daniella.sodre@ufpe.br) on 2015-03-13T13:23:12Z (GMT) No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) TESE Max Santana Rolemberg Farias.pdf: 3331146 bytes, checksum: aafe22682c1e4d4144f19615252785b9 (MD5) / Made available in DSpace on 2015-03-13T13:23:12Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) TESE Max Santana Rolemberg Farias.pdf: 3331146 bytes, checksum: aafe22682c1e4d4144f19615252785b9 (MD5) Previous issue date: 2014 / CNPq, FACEPE / O crescente número de tarefas em execução em plataformas Multiprocessor Systemson- Chips (MPSoC) exige mais e mais processadores e as plataformas MPSoC que utilizam o meio de comunicação tradicional (barramento) possui uma largura de banda limitada e não são escaláveis para projetos de alta performance. Nesse sentido, os MPSoC baseados em Networkon- Chip (NoC) foram propostos para resolver estas limitações. Um dos principais problemas em plataformas MPSoC baseado em NoC é o custo de comunicação, pois esse custo de comunicação depende do mapeamento de tarefas nos processadores. Este trabalho apresenta uma abordagem que utiliza uma meta-heurística para atribuir um conjunto de tarefas a um conjunto de Processing Element (PE) em um MPSoC baseado em NoC. Esta abordagem proposta avalia e otimiza o mapeamento de tarefas de aplicações e, em alguns experimentos, os resultados foram comparados com o pior e o melhor mapeamento do espaço de projeto. Os resultados encontrados durante os experimentos mostram uma redução média de energia de 47% quando é utilizado o mecanismo de agrupamento de tarefas e 44% quando o mecanismo de agrupamento é desligado.

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

The rapidly advancing high-throughput and next generation sequencing technologies facilitate deeper insights into the molecular mechanisms underlying the expression of phenotypes in living organisms. Experimental data and scientific publications following this technological advancement have rapidly accumulated in public databases. Meaningful analysis of currently available data in genomic databases requires sophisticated computational tools and algorithms, and presents considerable challenges to molecular biologists without specialized training in bioinformatics. To study their phenotype of interest molecular biologists must prioritize large lists of poorly characterized genes generated in high-throughput experiments. To date, prioritization tools have primarily been designed to work with phenotypes of human diseases as defined by the genes known to be associated with those diseases. There is therefore a need for more prioritization tools for phenotypes which are not related with diseases generally or diseases with which no genes have yet been associated in particular. Chromatin immunoprecipitation followed by next generation sequencing (ChIP-Seq) is a method of choice to study the gene regulation processes responsible for the expression of cellular phenotypes. Among publicly available computational pipelines for the processing of ChIP-Seq data, there is a lack of tools for the downstream analysis of composite motifs and preferred binding distances of the DNA binding proteins. This thesis is aimed to address the gap existing in the tools available to process high-throughput ChIP-Seq data to provide rapid analysis and interpretation of large lists of poorly characterized genes. Additionally, programs for the analysis of preferred binding distances of transcription factors were integrated into the pipeline for expedited results. A gene prioritization algorithm linking genes to non-disease phenotypes described by meaningful keywords was developed. This algorithm can be used to process candidate genetic targets of a transcription factor produced by a computational pipeline for ChIP-Seq data analysis.

Continuous progress in the nanotechnology field has allowed for the emergence of powerful, nanopore-based detection technology. Solid-state nanopores were developed for next-generation sequencing and single-molecule detection. They are advantageous over their biological counterpart because they offer robustness, stability, tunable pore size and the ability to be integrated within a microfluidic device. With all of these attractive attributes, solid-state nanopores are a top contender for point-of-care diagnostic technologies. However, hindering their performance is an inability to distinguish between small molecules, pore-clogging, and the detection rate's dependence on sample concentration. The concentration-dependent detection rate becomes particularly evident at low sample concentrations (<1 nM), sometimes taking hours for the nanopore to sense a single molecule because of diffusion. The inability to distinguish between small molecules can be addressed using DNA nanostructures; however, pore-clogging and variable detection rates hinder its potential in a clinical setting. This thesis proposes a microfluidic device design and methodology that seeks to mitigate pore-clogging and improve the detection rate for dilute samples. DNA coated microbeads will create a bead column within the microfluidic device and confine the target molecules to an extremely small (20 nL) volume. The sample can be washed, ridding the contaminants, and eluted on-chip, so the sample is purified and concentrated, affording a more reliable sensing performance. First, a magnetic microbead DNA assay was optimized off-chip, and the capture and release efficiencies were monitored using a Biotek™ Epoch™ 2 spectrophotometer (Chapter 2). Next, a novel microfluidic device design was optimized and validated to ensure precise sample manipulation (Chapter 3). Finally, the microbead assay was incorporated into the microfluidic device for sample concentration (Chapter 4). Fluorescence microscopy results suggest successful DNA elution from the microbeads within the microfluidic device, allowing for a 28.5 X concentration increase. This platform shows promise for sample preconcentration by reducing the starting DNA sample volume of 25 µL to 20 nL, which could improve the speed of solid-state nanopore sensing.

archives@tulane.edu / 1 / Owen Richfield

Many functions in a lab-on-a-chip device such as heating, electrochemical sensing and electrophoresis require integration of microelectrodes. However, conventional techniques for microelectrode integration are either requiring expensive facilities, cleanroom environment or insufficient in resolution and microelectrode thickness. Microwires have also been integrated into LOC devices as microelectrodes. They are commercially available in a diversity of material. and diameter, with industrial production standard and mechanical strength comparable to bulk metal, which make them ideal candidate for microelectrode. Nonetheless a technique to integrate these microwires into complicated microelectrode patterns has not yet been developed. In this thesis, two microwire integration techniques based on xurography are developed for elastomer and rigid polymer. Copper, silver, platinum, carbon and Ni-Cr alloy microwires down to 15 µm with minimum spacing of 150 µm and controllable position in the height direction are successfully integrated. The microwire electrode can also be suspended in the middle of the microchannel with desired length and angle. Various applications are presented to demonstrate the versatility of the xurographic microwire integration process. / Thesis / Master of Applied Science (MASc)

No description available.

The blood-brain barrier (BBB) is composed of brain microvascular endothelial cells (BMECs), pericytes, and astrocytic endfeet, which regulate the transport of molecules into and out of the brain. BMECs possess intrinsic barrier properties that limit the passage of approximately 98% of small molecules into the brain in healthy individuals. However, in some brain diseases, the BBB undergoes structural and functional alterations, which can contribute to disease progression. In this study, we aimed to investigate the BBB by exploring the effects of endothelial cell stretching and the optimal dimensionality of stretching to enhance endothelium barrier tightness in Chapter 2. Subsequently, we developed an endothelium gradient stretching device to further examine the stretching effect in Chapter 3. Additionally, we investigated the promotion of endothelium tightness through the use of electrospun fibers, wherein we controlled the pore size. Based on these findings, we designed and fabricated an organ chip model that incorporates mechanical stretching, microfluidic techniques, electrospun fibers, and hydrogel extracellular matrix (ECM). The results of permeability testing demonstrated that this chip significantly improved the tightness of microvascular selective transport ability and has the potential to be used in drug sorting for central nervous system (CNS) diseases.

Abstract Prediction of chip-breaking in machining is an important task for automated manufacturing. There are chip-breaking limits in machining chip-breaking chart, which determine the chip-breaking range. This thesis presents a study of the effect of 3-D groove insert parameters on chip breaking chart. Based on the chip-breaking criteria, the critical feed rate is formulated through an analysis of up-curl chip formation for 3-D grooves. Also in order to predict chip-breaking limits, for protruded insert grooves in finish machining, analytical models are established. In the analytical models, minimum and maximum depth of cut are identified for using different chip breaking models. As well insert nose radius effects on chip thickness for small depth of cut are studied. In the end, the analytical critical feed rate model is extended to finish machining with 3-D chipbreaking grooves.