The crisis of technology scaling led the industry of semiconductors towards the adoption of disruptive technologies and innovations to sustain the evolution of microprocessors and keep under control the timing of the design cycle. Multi-core and many-core architectures sought more energy-efficient computation by replacing a power-hungry processor with multiple simpler cores exploiting parallelism. Multi-core processors alone, however, turned out to be insufficient to sustain the ever growing demand for energy and power-efficient computation without compromising performance. Therefore, designers were pushed to drift from homogeneous architectures towards more complex heterogeneous systems that employ the large number of available transistors to incorporate a combination of customized energy-efficient accelerators, along with the general-purpose processor cores. Meanwhile, enhancements in manufacturing processes allowed designers to move a variety of peripheral components and analog devices into the chip. This paradigm shift defined the concept of {\em system-on-chip} (SoC) as a single-chip design that integrates several heterogeneous components. The rise of SoCs corresponds to a rapid decrease of the opportunity cost for integrating accelerators. In fact, on one hand, employing more transistors for powerful cores is not feasible anymore, because transistors cannot be active all at once within reasonable power budgets. On the other hand, increasing the number of homogeneous cores incurs more and more diminishing returns. The availability of cost effective silicon area for specialized hardware creates an opportunity to enter the market of semiconductors for new small players: engineers from several different scientific areas can develop competitive algorithms suitable for acceleration for domain-specific applications, such as multimedia systems, self-driving vehicles, robotics, and more. However, turning these algorithms into SoC components, referred to as {\em intellectual property}, still requires expert hardware designers who are typically not familiar with the specific domain of the target application. Furthermore, heterogeneity makes SoC design and programming much more difficult, especially because of the challenges of the integration process. This is a fine art in the hands of few expert engineers who understand system-level trade-offs, know how to design good hardware, how to handle memory and power management, how to shape and balance the traffic over an interconnect, and are able to deal with many different hardware-software interfaces. Designers need solutions enabling them to build scalable and heterogeneous SoCs. My thesis is that {\em the key to scalable SoC designs is a regular and flexible architecture that hides the complexity of heterogeneous integration from designers, while helping them focus on the important aspects of domain-specific applications through a companion system-level design methodology.} I open a path towards this goal by proposing an architecture that mitigates heterogeneity with regularity and addresses the challenges of heterogeneous component integration by implementing a set of {\em platform services}. These are hardware and software interfaces that from a system-level viewpoint give the illusion of working with a homogeneous SoC, thus making it easier to reuse accelerators and port applications across different designs, each with its own target workload and cost-performance trade-off point. A companion system-level design methodology exploits the regularity of the architecture to guide designers in implementing their intellectual property and enables an extensive design-space exploration across multiple levels of abstraction. Throughout the dissertation, I present a fully automated flow to deploy heterogeneous SoCs on single or multiple field-programmable-gate-array devices. The flow provides non-expert designers with a set of knobs for tuning system-level features based on the given mix of accelerators that they have integrated. Many contributions of my dissertation have already influenced other research projects as well as the content of an advanced course for graduate and senior undergraduate students, which aims to form a new generation of system-level designers. These new professionals need not to be circuit or register-transfer level design experts, and not even gurus of operating systems. Instead, they are trained to design efficient intellectual property by considering system-level trade-offs, while the architecture and the methodology that I describe in this dissertation empower them to integrate their components into an SoC. Finally, with the open-source release of the entire infrastructure, including the SoC-deployment flow and the software stack, I hope I will be able to inspire other research groups and help them implement ideas that further reduce the cost and design-time of future heterogeneous systems.

Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of delay and power increase of on-chip interconnects. This thesis aims to characterize and optimize several basic low-swing interconnect circuits, by developing simple delay and power estimation methodologies. Accuracies of the proposed methods are validated against SPICE-based simulations on the 90nm technology node. Based on the delay and power estimation methods developed, optimum power-delay trade-off curves are obtained and directly used for comparison among different interconnect circuit strategies. Three low-swing techniques are included, i.e. conventional level converter (CLC), pseudodifferential interconnect circuit (PDIFF), and current-mode signaling (CM). These techniques represent significantly different driver and receiver topologies, where CLC uses lower supply voltage of a normal inverter driver, PDIFF uses NMOS only drivers, while CM has a low impedance termination at the receiving end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. A simplified repeater performance estimation technique considering ramp input signals is also proposed. The most important step in estimating delay of different driver circuits is the accurate estimation of transistor effective resistance, which considers velocity saturation effects and voltage transition patterns. Optimization for the CM circuit for on-chip interconnects requires completely different treatment than the voltage-mode circuits, due to the different and more complex effective driver resistance and termination resistance modeling. Sizing the driver and receiver transistors should be done simultaneously as their resistive values which affect its performance are dependent on each other. Optimum transistor sizing is very dependenton the required voltage swing chosen. Results of our comparisons show that optimized CLC (reduced voltage supply) repeaters appears to give the best general performance with a slight delay overhead compared to full-swing repeaters. The fact that CLC with repeaters has shorter delay than single-segment CM and PDIFF highlights the effectiveness of repeater structures in long wires. The inclusion of inductance and closed-form solutions to derive optimum transistor sizings for various low-swing interconnect circuits may be developed as a future work using delay and power estimation models presented in this thesis, which is a challenging task to do considering the non-linear equations involved.

Thesis (M.S. in computer engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 54-58).

<p> </p><p>The deep sub micron process technology and application convergence increases the design challenges in System-on-Chip (SoC). The traditional bus based on chip communication are not scalable and fails to deliver the performance requirements of the complex SoC. The Network on Chip (NoC) has been emerged as a solution to address these complexities of a efficient, high performance, scalable SoC design. The Aethereal NoC provides the latency and throughput bounds by pipelined timedivision multiplexed (TDM) circuit switching architecture. A global synchronous clock defines the timing for TDM, which is not beneficial for decreasing process geometry and increasing clock frequency. This thesis work focuses on the Aelite NoC architecture. The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements. The Aelite NoC implements flit synchronous communication using mesochronous and asynchronous links.</p><p> </p><p> </p>

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

The last two decades have witnessed the birth of revolutionary technologies in data communications including wireless technologies, System on Chip (SoC), Multi Processor SoC (MPSoC), Network on Chip (NoC), and more. At the same time we have witnessed that performance does not always keep pace with expectations in many services like multimediaservices and biomedical applications. Moreover, the IT market has suffered from some crashes. Hence, this triggered us to think of making use of available technologies and developing new ones so that the performance level is suitable for given applications and services. In the medical field, from a statistical viewpoint, the biggest diseases in number of deaths are heart diseases, namely Cardiovascular Disease (CVD) and Stroke. The application with the largest market for CVD is the electrocardiogram (ECG/EKG) analysis. According to the World Health Organization (WHO) report in 2003, 29.2% of global deaths are due to CVD and Stroke, half of which could be prevented if there was proper monitoring. We found in the new advance in microelectronics, NoC, SoC, and MPSoC, a chance of a solution for such a big problem. We look at the communication technologies, wireless networks, and MPSoC and realize that many projects can be founded, and they may affect people's lives positively, as for example, curing people more rapidly, as well as homecare of such large scale diseases. These projects have a medical impact as well as economic and social impacts. The intention is to use performance analysis of interconnected microelectronic systems and combine it with MPSoC and NoC technologies in order to evolve to new systems on chip that may make a difference. Technically, we aim at rendering more computations in less time, on a chip with smaller volume, and with less expense. The performance demand and the vision of having a market success, i.e. contributing to lower healthcare costs, pose many challenges on the hardware/software co-design to meet these goals. This calls upon the development of new integrated circuits featuring increased energy efficiency while providing higher computation capabilities, i.e. better performance. The biomedical application of ECG analysis is an ideal target for an application-specific SoC implementation. However, new 12-lead ECG analyses algorithms are needed to meet the aforementioned goals. In this thesis, we present two novel algorithms for ECG analysis, namely the Autocorrelation-Function (ACF) based algorithm and the Fast Fourier Transform (FFT) based algorithm. In this respect, we explore the design space by analyzing different hardware and software architectures. As a result, we realize a design with twelve processors that can compute 3.5 million arithmetic computations and respect the real time hard deadline for our biomedical application (3.5-4seconds), and that can deploy the ACF-based and FFT-based algorithms. Then, we investigate the configuration space looking for the most effective solution, performance and energy-wise. Consequently, we present three interconnect architectures (Single Bus, Full Crossbar, and Partial Crossbar) and compare them with existing solutions. The sampling frequencies of 2.2 KHz and 4 KHz, with 12 DSPs, are found to be the critical points for our Shared-Bus design and Crossbar architecture, respectively. We also show how our performance analysis methods can be applied to such a field of SoC design and with a specific purpose application in order to converge to a solution that is acceptable from a performance viewpoint, meets the real-time demands, and can be implemented with the present technologies while at the same time paving the way for easier and faster development. In order to connect our MPSoC solution to communication networks to transmit the medical results to a healthcare center, we come up with new protocols that will allow the integration of multiple networks on chips in a communication network. Finally, we present a methodology for HW/SW Codesign for application-specific systems (with focus on biomedical applications) that require a large number of computations since this will foster the convergence to solutions that are acceptable from a performance point of view. / QC 20100624

Lab-on-a-chip (LOC) biological assays have the potential to fundamentally reform healthcare. The move away from centralized facilities to Point-of-Care (POC) testing of biological assays would improve the speed and accuracy of these, thereby improving patient care. Before LOC can be realized, a number of challenges must be addressed: the need for expert users must be abstracted away; the manufacturing cost of $5 per test threshold must be met; and the supporting infrastructure must be integrated down to an easily portable size. These challenges can be addressed with the deposition of microfluidics on CMOS chips. By designing application specific integrated circuits (ASICs) much of the automation and the supporting infrastructure needed to run these assays can be integrated into the chip. Additionally, CMOS fabrication is some of the most optimized manufacturing in industry today. One of the central challenges with LOC on ASIC is the signal acquisition from the microfluidics into the CMOS. Optical sensing of fluorescence is one form of sensing used for LOC assays. Despite a large literature, there has not been a strong demonstration of monolithic LOC fluorescence detection (FD) for low concentration samples. This work explores the limit-of-detection (LOD) for LOC FD through analysis of the signal and noise of a proposed acquisition channel. The proposed signal acquisition channel consists of an on chip photodiode and integrator based amplification circuits. A hand analysis of the signal propagation through the channel and the noise sources introduced by the circuitry, is performed. This analysis is used to establish relationships between different circuit parameters and the LOD of a hypothetical LOC device. The hand analysis is verified through simulation and the acquisition channel is implemented in: (i) the Austrian Microsystems 350nm CMOS process, (ii) discrete components. Testing of the CMOS chip revealed several issues not identified in extracted simulation; however, the discrete integrator demonstrated many of the trends predicted by the hand analysis and simulations and achieved a LOD of 7.2$\mu M$. This analysis provides insight into the engineering trade-offs required to improve the LOD, to enable more wide spread application of LOC FD.

This thesis was on the development of a high-throughput electrokinetically-controlled heterogeneous immunoassay (EK-IA) microfluidic chip for clinical application. Through a series of experimental studies, a high-throughput EK-IA was developed. This EK-IA was capable of automatically screening multiple analytes from up to 10 samples in parallel, in only 26 min. Flow control in an integrated microfluidic network was realized by numerical simulation of the transport processes. This EK-IA was successfully applied to detect E. coli O157:H7 antibody and H. pylori antibody from human sera with satisfactory accuracy. Simultaneous screening of both antibodies from human sera was also achieved, demonstrating the potential of this EK-IA for efficiently detecting multiple pathogenic infections in clinical settings. Preliminary work on the application of EK-IA to detect biomarkers of embryo development in embryo culture media also yielded good results. In addition to the experimental studies, the reaction kinetics of this microfluidic EK-IA has also been investigated, using both numerical simulation and a modified Damköhler number. Targeted towards a more sensitive assay, the influences of several important parameters on the reaction kinetics were studied. This EK-IA holds great promise for automated and high-throughput immunoassay in clinical environments.

Introduction: Hypertension is the number one risk factor for cardiovascular diseases. Total peripheral resistance (TPR) is strongly involved in blood pressure homeostasis. TPR is primarily determined by resistance arteries (RAs). Pathogenic factors which change RA structure are associated with cardiovascular disease. Despite this, methods employed in the study of RAs lack efficiency. Methods: A polymer microfluidic device (Artery-on-a-Chip Device, AoC) made from polydimethylsiloxane (PDMS) was developed. RAs from CD1 mice were measured on the device. Their responses to phenylephrine (PE), acetylcholine (Ach), FURA-2 imaging, and 24-h culture were assessed. Results: Following several modifications, vessel function on the AoC device was successfully measured. Robust PE constriction and Ach-induced vasodilation were observed. AoC arteries were viable after 24-hour culture, and FURA-2 was successfully imaged. Conclusions: The AoC device is a viable alternative to cannulation myography. The AoC can greatly increase the efficiency of RA studies, while also decreasing training time and difficulty.

Smartphone/tablet Systems-on-Chip (SoCs) integrate increasing number of components to offer more functionality. Capacity and efficiency of data communication between memory and other hardware blocks have become a major concern in the SoC design. To address this concern, we propose to use Network-on-Chip (NoC) architectures, to meet high bandwidth, and low power and area demands. We propose a Quality-of-Service (QoS) scheme to differentially provision network resources to cater to different performance requirements by different hardware blocks. Implementation and evaluation are performed on a simulation infrastructure we construct specifically for this type of SoCs. We demonstrate, via simulation results, that the proposed Dynamic QoS schemes can achieve better bandwidth provisioning, with good area and power efficiencies.