THz spectroscopy is an emerging technique for studying the dynamics and interactions of cells and biomolecules, but many practical challenges still remain in experimental studies. We present a prototype of simple and inexpensive cell-trapping microfluidic chip for THz spectroscopic study of live cells. Cells are transported, trapped and concentrated into the THz exposure region by applying an AC bias signal while the chip maintains a steady temperature at 37 degrees C by resistive heating. We conduct some preliminary experiments on E. coli and T-cell solution and compare the transmission spectra of empty channels, channels filled with aqueous media only, and channels filled with aqueous media with un-concentrated and concentrated cells.

No description available.

The past decade has shown distinct advances in the theory of multiple input multi output techniques for wireless communication systems. Now, the time has come to demonstrate this progress in terms of applications. This thesis introduces implementation of Schnorr- Euchner strategy based decoding algorithm applied on Altera system-on-chip (Stratix EP1S10F780C6) with Nios embedded processor. The lattice decoder is developed on FPGA using VHDL. The preprocessing part of algorithm is targeted for Nios embedded processor using C language. A controller is also designed to interface and communicate between the Nios embedded processor and lattice decoder.

Featured with good scalability, modularity and large bandwidth, Network-on-Chip (NoC) has been widely applied in manycore Chip Multiprocessor (CMP) and Multiprocessor System-on-Chip (MPSoC) architectures. The provision of guaranteed service emerges as an important NoC design problem due to the application requirements in Quality-of-Service (QoS). Formal analysis of performance bounds plays a critical role in ensuring guaranteed service of NoC by giving insights into how the design parameters impact the network performance. The study in this thesis proposes analysis methods for delay and backlog bounds with Network Calculus (NC). Based on xMAS (eXecutable Micro-Architectural Specification), a formal framework to model communication fabrics, the delay bound analysis procedure is presented using NC. The micro-architectural xMAS representation of a canonical on-chip router is proposed with both the data flow and control flow well captured. Furthermore, a well-defined xMAS model for a specific application on an NoC can be created with network and flow knowledge and then be mapped to corresponding NC analysis model for end-to-end delay bound calculation. The xMAS model effectively bridges the gap between the informal NoC micro-architecture and the formal analysis model. Besides delay bound, the analysis of backlog bound is also crucial for predicting buffer dimensioning boundary in on-chip Virtual Channel (VC) routers. In this thesis, basic buffer use cases are identified with corresponding analysis models proposed so as to decompose the complex flow contention in a network. Then we develop a topology independent analysis technique to convey the backlog bound analysis step by step. Algorithms are developed to automate this analysis procedure. Accompanying the analysis of performance bounds, tightness evaluation is an essential step to ensure the validity of the analysis models. However, this evaluation process is often a tedious, time-consuming, and manual simulation process in which many simulation parameters may have to be configured before the simulations run. In this thesis, we develop a heuristics aided tightness evaluation method for the analytical delay and backlog bounds. The tightness evaluation is abstracted as constrained optimization problems with the objectives formulated as implicit functions with respect to the system parameters. Based on the well-defined problems, heuristics can be applied to guide a fully automated configuration searching process which incorporates cycle-accurate bit-accurate simulations. As an example of heuristics, Adaptive Simulated Annealing (ASA) is adopted to guide the search in the configuration space. Experiment results indicate that the performance analysis models based on NC give tight results which are effectively found by the heuristics aided evaluation process even the model has a multidimensional discrete search space and complex constraints. In order to facilitate xMAS modeling and corresponding validation of the performance analysis models, the thesis presents an xMAS tool developed in Simulink. It provides a friendly graphical interface for xMAS modeling and parameter configuring based on the powerful Simulink modeling environment. Hierarchical model build-up and Verilog-HDL code generation are essentially supported to manage complex models and conduct simulations. Attributed to the synthesizable xMAS library and the good extendibility, this xMAS tool has promising use in application specific NoC design based on the xMAS components. / <p>QC 20150520</p>

Magnetic nanoparticle (MNP) combined with biomolecules in a microfluidic system can be efficiently used in various applications such as mixing, pre-concentration, separation and detection. They can be either integrated for point-of care applications or used individually in the area of bio-defense, drug delivery, medical diagnostics, and pharmaceutical development. The interaction of magnetic fields with magnetic nanoparticles in microfluidic flows will allow simplifying the complexity of the present generation separation and detection systems. The ability to understand the dynamics of these interactions is a prerequisite for designing and developing more efficient systems. Therefore, in this work proof-of-concept experiments are combined with advanced numerical simulation to design, develop and optimize the magnetic microfluidic systems for mixing, separation and detection. Different strategies to combine magnetism with microfluidic technology are explored; a time-dependent magnetic actuation is used for efficiently mixing low volume of samples whereas tangential microfluidic channels were fabricated to demonstrate a simple low cost magnetic switching for continuous separation of biomolecules. A simple low cost generic microfluidic platform is developed using assembly of readily available permanent magnets and electromagnets. Microfluidic channels were fabricated at much lower cost and with a faster construction time using our in-house developed micromolding technique that does not require a clean room. Residence-time distribution (RTD) analysis obtained using dynamic light scattering data from samples was successfully used for the first time in microfluidic system to characterize the performance. Both advanced multiphysics finite element models and proof of concept experimentation demonstrates that MNPs when tagged with biomolecules can be easily manipulated within the microchannel. They can be precisely captured, separated or detected with high efficiency and ease of operation. Presence of MNPs together with time-dependent magnetic actuation also helps in mixing as well as tagging biomolecules on chip, which is useful for point-of-care applications. The advanced mathematical model that takes into account mass and momentum transport, convection & diffusion, magnetic body forces acting on magnetic nanoparticles further demonstrates that the performance of microfluidic surface-based bio-assay can be increased by incorporating the idea of magnetic actuation. The numerical simulations were helpful in testing and optimizing key design parameters and demonstrated that fluid flow rate, magnetic field strength, and magnetic nanoparticle size had dramatic impact on the performance of microfluidic systems studied. This work will also emphasize the importance of considering magnetic nanoparticles interactions for a complete design of magnetic nanoparticle-based Lab-on-a-chip system where all the laboratory unit operations can be easily integrated. The strategy demonstrated in this work will not only be easy to implement but also allows for versatile biochip design rules and provides a simple approach to integrate external elements for enhancing mixing, separation and detection of biomolecules. The vast applications of this novel concept studied in this work demonstrate its potential of to be applied to other kinds of on-chip immunoassays in future. We think that the possibility of integrating magnetism with microfluidic-based bioassay on a disposable chip is a very promising and versatile approach for point-of care diagnostics especially in resource-limited settings.

Asphalt pavements often experience premature distresses caused by extreme environmental condition of both high and low temperatures. By maintaining a stable temperature a potentially longer lasting pavement is achievable. Laboratory tests and a field study were conducted on Hot Mix Asphalt pavements using a Geosynthetic Reinforced Chip Seal (GRCS); the temperature data from the two tests were compared for the GRCS’s effectiveness in reducing the pavement high temperatures. It was found that using a GRCS with an asphalt saturated geosynthetic layer and a chip seal with high reflectivity aggregates is an effective way to reduce high temperatures at different depths in the pavements. Field studies showed a temperature reduction of 9.2OC at the original surface and 10.3OC at 12.5 mm below the original surface, for an air temperature of 49OC.

Droplet-based microfluidics can be used to enhance stem cell-based therapy by creating cell-laden hydrogel encapsulations to increase engraftment and retention while providing protection from immune responses caused by the host environment. Current research involves gaining better control over therapeutic mechanisms and one focus is to understand the mechanisms behind cell egress. Control over egress is vital to determining how long cells remain in proximity to the therapeutic target. We propose a microfluidic platform capable of encapsulating cells in two subsequent steps in order to create a double emulsion structure around the cell. In this project, hydrogel-in-hydrogel microdroplets are successfully manufactured without the presence of an intermediate oil layer and are used to observe model NIH 3T3 cell egress. In studying cell egress from singly or doubly encapsulated microcapsules, we are able to better understand the mechanisms that drive egress. Specifically, we hypothesize that cells egress when close to the edge of the microcapsule. In a double emulsion, cells are naturally located away from the edge and closer to the center. Results show that double emulsion microdroplets significantly reduce cell egress but do not eliminate it.

As digital systems continue to grow in complexity, the design of conventional synchronous systems is facing unprecedented challenges. The number of transistors on individual chips is already in the multi-billion range, and a greatly increasing number of components are being integrated onto a single chip. As a consequence, modern digital designs are under strong time-to-market pressure, and there is a critical need for composable design approaches for large complex systems. In the past two decades, networks-on-chip (NoC’s) have been a highly active research area. In a NoC-based system, functional blocks are first designed individually and may run at different clock rates. These modules are then connected through a structured network for on-chip global communication. However, due to the rigidity of centrally-clocked NoC’s, there have been bottlenecks of system scalability, energy and performance, which cannot be easily solved with synchronous approaches. As a result, there has been significant recent interest in combing the notion of asynchrony with NoC designs. Since the NoC approach inherently separates the communication infrastructure, and its timing, from computational elements, it is a natural match for an asynchronous paradigm. Asynchronous NoC’s, therefore, enable a modular and extensible system composition for an ‘object-orient’ design style. The thesis aims to significantly advance the state-of-art and viability of asynchronous and globally-asynchronous locally-synchronous (GALS) networks-on-chip, to enable high-performance and low-energy systems. The proposed asynchronous NoC’s are nearly entirely based on standard cells, which eases their integration into industrial design flows. The contributions are instantiated in three different directions. First, practical acceleration techniques are proposed for optimizing the system latency, in order to break through the latency bottleneck in the memory interfaces of many on-chip parallel processors. Novel asynchronous network protocols are proposed, along with concrete NoC designs. A new concept, called ‘monitoring network’, is introduced. Monitoring networks are lightweight shadow networks used for fast-forwarding anticipated traffic information, ahead of the actual packet traffic. The routers are therefore allowed to initiate and perform arbitration and channel allocation in advance. The technique is successfully applied to two topologies which belong to two different categories – a variant mesh-of-trees (MoT) structure and a 2D-mesh topology. Considerable and stable latency improvements are observed across a wide range of traffic patterns, along with moderate throughput gains. Second, for the first time, a high-performance and low-power asynchronous NoC router is compared directly to a leading commercial synchronous counterpart in an advanced industrial technology. The asynchronous router design shows significant performance improvements, as well as area and power savings. The proposed asynchronous router integrates several advanced techniques, including a low-latency circular FIFO for buffer design, and a novel end-to-end credit-based virtual channel (VC) flow control. In addition, a semi-automated design flow is created, which uses portions of a standard synchronous tool flow. Finally, a high-performance multi-resource asynchronous arbiter design is developed. This small but important component can be directly used in existing asynchronous NoC’s for performance optimization. In addition, this standalone design promises use in opening up new NoC directions, as well as for general use in parallel systems. In the proposed arbiter design, the allocation of a resource to a client is divided into several steps. Multiple successive client-resource pairs can be selected rapidly in pipelined sequence, and the completion of the assignments can overlap in parallel. In sum, the thesis provides a set of advanced design solutions for performance optimization of asynchronous and GALS networks-on-chip. These solutions are at different levels, from network protocols, down to router- and component-level optimizations, which can be directly applied to existing basic asynchronous NoC designs to provide a leap in performance improvement.

The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment. The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity. The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes. The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes. To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s.

Liu, Zhouyi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 110-114). / Abstracts in English and Chinese. / ABSTRACTS --- p.I / 摘要 --- p.II / CONTENTS --- p.III / LIST OF FIGURE --- p.V / LIST OF TABLE --- p.VI / ACKNOWLEDGEMENT --- p.VII / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- NETWORK-ON-CHIP --- p.1 / Chapter 1.2 --- RELATED WORKS --- p.2 / Chapter 1.3 --- PLATFORM OVERVEW --- p.6 / Chapter 1.4 --- AUTHOR'S CONTRIBUTION --- p.10 / Chapter CHAPTER 2 --- NOC LIBRARY --- p.12 / Chapter 2.1 --- NETWORK TERMINOLOGY --- p.12 / Chapter 2.2 --- BASIC STRUCTURE --- p.15 / Chapter 2.3 --- LOW-POWER ORIENTED ARCHITECTURE --- p.20 / Chapter 2.3.1 --- Low-Cost Allocator Design --- p.21 / Chapter 2.3.2 --- Clock Gating --- p.22 / Chapter 2.3.3 --- Express Virtual Channel Insertion --- p.22 / Chapter 2.4 --- LOW-LATENCY ORIENTED ARCHITECTURE --- p.28 / Chapter 2.4.1. --- Lookahead Bypass Scheme --- p.29 / Chapter 2.4.2. --- Lookahead Bypass Router Architecture --- p.29 / Chapter CHAPTER 3 --- BENCHMARK AND MEASUREMENT --- p.31 / Chapter 3.1 --- BENCHMARK GENERATION --- p.32 / Chapter 3.1.1 --- Types of Traffic Patterns --- p.32 / Chapter 3.1.2 --- Traffic Generator --- p.36 / Chapter 3.2 --- MEASUREMENT SETTING --- p.38 / Chapter 3.2.1 --- Warming-up Period. --- p.38 / Chapter 3.2.2 --- Latency Definition --- p.39 / Chapter 3.2.3 --- Throughput Definition --- p.40 / Chapter 3.2.4 --- Virtual Channel Utilization --- p.40 / Chapter CHAPTER 4 --- PLATFORM STRUCTURE --- p.41 / Chapter 4.1 --- FILE TREE --- p.42 / Chapter 4.1.1 --- System Files --- p.46 / Chapter 4.1.2 --- Low-Power NoC Related --- p.47 / Chapter 4.1.3 --- Low-Latency NoC Related --- p.50 / Chapter 4.1.4 --- Project Related --- p.51 / Chapter 4.2 --- PROCESSES --- p.52 / Chapter 4.3 --- GUI ACCESS --- p.56 / Chapter 4.3.1 --- Section 1: Project Setup --- p.58 / Chapter 4.3.2 --- Section 2-a: Low-Power Router Structure --- p.59 / Chapter 4.3.3 --- Section 2-b: Low-Latency Router Structure --- p.60 / Chapter 4.3.4 --- Section 3: Benchmark & Measurement --- p.60 / Chapter 4.3.5 --- Section 4: View Result --- p.62 / Chapter 4.3.6 --- Low-Power NoC Example --- p.62 / Chapter CHAPTER 5 --- OPTIMIZATION AND COMPARISON --- p.72 / Chapter 5.1 --- OPTIMIZATION TECHNIQUE --- p.72 / Chapter 5.1.1 --- Optimization Phase 1: Inactive Buffer Removal --- p.73 / Chapter 5.1.2 --- Optimization Phase 2: Infighting Analysis --- p.74 / Chapter 5.1.3 --- Over-Optimization --- p.75 / Chapter 5.1.4 --- Optimization Example --- p.79 / Chapter 5.2 --- NOCS COMPARISON --- p.83 / Chapter 5.3 --- LOW-POWER IMPLEMENTATION CODE EXPORT --- p.88 / Chapter CHAPTER 6 --- SUMMARY AND FUTURE WORK --- p.92 / Chapter 6.1. --- SUMMARY --- p.92 / Chapter 6.2. --- FUTURE WORK --- p.93 / REFERENCES --- p.95