Electromigration related damage in solder bumps is one of the emerging issues resulting from the fast scaling-down of features in semiconductor packages. Although the electromigration phenomenon has been intensively studied on silicon level interconnect lines since the late 1960s, it is far less understood in solder bumps. Electromigration in solder joints can be quite different from that of the interconnects due to the differences in material systems and structures. This study addressed the solder joint electromigration and contained three major objectives. The first objective of this study was to set up an effective experimental technique to examine the damage development and determine the time-to-failure in the electromigration tests. The structure and dimension of the flip chip solder bump is very different from that of the chip level interconnect. Consequently, the traditional failure tracking method based on 2-point resistance monitoring is no longer able to provide real-time damage evolution information. A test system based on a Wheat stone bridge circuit was introduced. The technique showed the capability of detecting milliohm resistance changes and could track the interfacial crack growth induced by electromigration damage. Other aspects of the experiment, such as temperature and current distribution inside the test structure, were also examined so that proper lifetime could be extrapolated from testing condition to normal working condition. The second objective was to examine the failure mechanisms in solder bump electromigration which could be significantly different between various solder bump systems. Pb-free and high-Pb solder alloys with different UBM configurations were studied. The research results showed that the most active region during solder bump electromigration was the under bump metallization (UBM) layer and its interface with the solder due to the intermetallic compound formation and UBM dissolution. Therefore, the electromigration-induced damage occurred mostly in this region. The failure mechanisms were found to be highly dependent on the material system as well as the temperature. The third objective was to determine the statistical lifetime of the flip chip solder bumps under electromigration. Lognormal distributions were used to fit the lifetime. The temperature and current dependence was assumed to follow Black's equation and the activation energies was calculated from that. The results showed that the traditional Black's equation might not be applicable to solder bump electromigration due to the different failure mechanism at different temperatures. Special attention is needed to set up design rules for maximum operating current and temperature for a solder bump structure when extrapolating data from high temperature. / text

Since the late 1990s our group has been working with groups in chemistry department at the University of Texas at Austin on a project referred as "Electronic Taste Chip," a MicroElectroMechanical System (MEMS) based miniaturized microfluidic chemical sensor with multianalyte detection capabilities. By integrating optical detection mechanism directly onto the silicon chip a cost effective, compact, and portable sensor can be realized enabling use of these chips out of conventional laboratory environment. Addition to the integration a noble approach of accessing a photodiode with non-contact powerless RFID type readout is presented. By doing so a packaged photodiode can be interrogated without direct electrical contact, enhancing the portability even further for a sensor operated in aqueous medium. First background information regarding the project as well as design and integration criteria is presented followed by demonstration of non-contact RFID-type readout of a photodiode. Detailed discussion on the development of process integration scheme is discussed along with the measurements verifying the performance of the fabricated photodiode. During this investigation normally overlooked design criteria of collection efficiency, the effect of how a target element is to be delivered to a detection mechanism on the overall performance of the sensor, is addressed and discussed.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

Todays modern warfare puts high demands on military equipment. Where soldiers are concerned, types of communication equipment such as radios, displays and headsets play a central role. A modern soldier is often required to maintain communication links with other military units. These units can, for example, consist of platoon commanders, headquarters and other soldiers. If the soldier needs to make a report to several units, the message needs to be sent to several radio networks that are connected to these separate units. This multiplicity in turn requires several items of radio equipment connected to the radio network frequencies. Considering all the communication equipment that is used by a modern soldier, the parallel data flow and all the weight a soldier needs to carry, can get quite extensive.  \noindentAt Saab AB it has been proven that a combination of powerful embedded hardware platforms and cross platform software fulfills the communication needs. However, the weight issue still remains as these embedded platforms are quite bulky and hard to carry. In order to increase the portability, a tailored Android application for smaller low-power embedded hardware platform has been developed at Saab AB. Saab AB has also developed a portable analogue interconnection unit for connecting three radios and a headset, the SKE (Sammankopplingsenhet). \noindentSaab AB intends to develop a new product for soldiers, the RPCS (Rugged Portable Communication System), with capacities of running the Android application and combining the audio processing functionality of the SKE. This thesis focuses on developing a hardware platform prototype for the RPCS using Beagleboard. The SKE audio processing functionality is developed as a software application running on the Beagleboard.

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The latest generation of fighter aircraft utilizes a 270Vdc power system [1]. Such high voltage DC power systems are difficult to protect with conventional circuit breakers because the current does not automatically go to zero twice per cycle during a fault like it does in an AC power system and thus arcing of the contacts is a problem. Solid state power controllers (SSPCs) are the solid state equivalent of a circuit breaker that do not arc and which can respond more rapidly to a fault than a mechanical breaker [2]. Present SSPCs are limited to lower voltages and currents by the available power semiconductors [8,9]. This dissertation presents design and experimental results for a SSPC that utilizes SiC power JFETs for the SSPC power switch to extend SSPC capability to higher voltages and currents in a space that is smaller than what is practically achievable with a Si power switch. The research started with the thermal analysis of the SSPCs power switch, which will guide the development of a SiC JFET multi-chip power module to be fabricated by Solid State Devices Inc. (SSDI) using JFETs from SiCED and/or Semisouth LLC. Multiple multi-chip power modules will be paralleled to make the SSPC switch. Fabricated devices were evaluated thermally both statically and dynamically and electrically both statically and dynamically. In addition to the SiC module research a detailed design of the high voltage SSPC control circuit capable of operating at 200andamp;ordm;C was completed including detailed analysis, modeling and simulations, detailed schematic diagrams and detailed drawings. Finally breadboards of selected control circuits were fabricated and tested to verify simulation results. Methods for testing SiC JFET devices under transient thermal conditions unique to the SSPC application was also developed.

Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of the wire length distribution increases with length and (ii) the use of Rent’s rule with a constant Rent’s exponent p, to calculate the terminal count of a given block size, limits the accuracy of the results from a macroscopic model. Therefore, a new model for the parameter p is developed to more accurately reflect the terminal count of a given block size in placement, and using this, a new more accurate macroscopic model is developed. In addition, a model to predict the variability is also incorporated into the macroscopic model. Studies to understand limitations to microscopic prediction reveal that (i) only a fraction of the wires in a given design are predictable, and these are mostly from shorter nets with smaller degrees and (ii) the current microscopic prediction models are built based on the assumption that a single metric could be used to accurately predict the individual length of all the wires in a design. In this thesis, an alternative microscopic model is developed for the predicting the shorter wires based on a hypothesis that there are multiple metrics that influence the length of the wires. Three different metrics are developed and fitted into a heuristic classification tree framework to provide a unified and more accurate microscopic model.

A novel large-scale silicon system platform with 9.6cm² of active silicon interposer area is demonstrated. The platform contains three interposer tiles and two silicon bridges, and a novel self-alignment technology utilizing positive self-alignment structures (PSAS) and a novel mechanically flexible interconnect (MFI) technology are developed and used to align and interconnect tiles and bridges on an FR4 substrate. An accurate alignment < 8μm between silicon bridges and interposer tiles makes it possible to accommodate nanophotonics to enable a high bandwidth and low-energy system in the future. In addition, mechanically flexible interconnects and silicon bridges are used to provide electrical connections between interposer tiles without having to use motherboard-level interconnects. Finally, an elastomeric bump interposer is developed to enable the packaging of PSAS-enabled silicon systems, and PSAS' compatibility with a thermo-compression bonding process is demonstrated to enable a wide range of system configurations involving interposer tiles and bridges, including the multi-chip package configuration used with the elastomeric bump interposers.

This thesis presents a link-level latency analysis for real-time network-on-chip interconnects that use priority-based wormhole switching. This analysis incorporates both direct and indirect interferences from other traffic flows, and it leverages pipelining and parallel transmission of data across the links. The resulting link-level analysis provides a tighter worst-case upper-bound than existing techniques, which we verify with our analysis and simulation experiments. Our experiments show that on average, link-level analysis reduces the worst-case latency by 28.8%, and improves the number of flows that are schedulable by 13.2% when compared to previous work.

Lab-on-a-chip (LOC) biological assays have the potential to fundamentally reform healthcare. The move away from centralized facilities to Point-of-Care (POC) testing of biological assays would improve the speed and accuracy of these, thereby improving patient care. Before LOC can be realized, a number of challenges must be addressed: the need for expert users must be abstracted away; the manufacturing cost of $5 per test threshold must be met; and the supporting infrastructure must be integrated down to an easily portable size. These challenges can be addressed with the deposition of microfluidics on CMOS chips. By designing application specific integrated circuits (ASICs) much of the automation and the supporting infrastructure needed to run these assays can be integrated into the chip. Additionally, CMOS fabrication is some of the most optimized manufacturing in industry today. One of the central challenges with LOC on ASIC is the signal acquisition from the microfluidics into the CMOS. Optical sensing of fluorescence is one form of sensing used for LOC assays. Despite a large literature, there has not been a strong demonstration of monolithic LOC fluorescence detection (FD) for low concentration samples. This work explores the limit-of-detection (LOD) for LOC FD through analysis of the signal and noise of a proposed acquisition channel. The proposed signal acquisition channel consists of an on chip photodiode and integrator based amplification circuits. A hand analysis of the signal propagation through the channel and the noise sources introduced by the circuitry, is performed. This analysis is used to establish relationships between different circuit parameters and the LOD of a hypothetical LOC device. The hand analysis is verified through simulation and the acquisition channel is implemented in: (i) the Austrian Microsystems 350nm CMOS process, (ii) discrete components. Testing of the CMOS chip revealed several issues not identified in extracted simulation; however, the discrete integrator demonstrated many of the trends predicted by the hand analysis and simulations and achieved a LOD of 7.2$\mu M$. This analysis provides insight into the engineering trade-offs required to improve the LOD, to enable more wide spread application of LOC FD.