Universiẗat, Diss., 2004--Münster (Westfalen).

Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Systems Science Dept., 2004 / Only abstract available. "At the request of the author, this graduate work is not available for purchase." Includes bibliographical references.

Le suivi de la qualité de l'eau a été d'une grande importance depuis ces dernières décennies afin de trouver des solutions de contrôler la contamination de l'eau, induite en grande partie par les activités agricoles et industrielles. Bien que les méthodes conventionnelles, comme la chromatographie, sont des outils très précis et sensibles, un intérêt grandissant a été placé sur des techniques prometteuses qui peuvent être utilisées sur site, sont bas coût, et offrent la possibilité d'effectuer des analyses rapides. Le travail présenté ici est dédié au développement de composant Laboratoire sur Puce pour l'analyse de la toxicité de l'eau. Il consiste en un système portable pour la détection sur site et offre la possibilité d'une double détection complémentaire : optique et électrochimique. Comme la partie dédiée au capteur électrochimique a préalablement été validée, cette étude est focalisée sur l'implémentation d'un biocapteur électrochimique basé sur l'utilisation d'une algue, pour la détection de polluants dans l'eau. Le principe basique de détection consiste au suivi de changements de l'activité métabolique d'algues induits par la présence d'herbicides. La réponse de l'algue est différente pour chaque concentration d'herbicide dans un échantillon examiné. Deux herbicides sélectionnés affectent l'activité photosynthétique de l'algue et par conséquent, induisent des modifications dans la quantité des espèces électroactives produites par l'algue : O2, H2O2 et H3O+/OH-. Avant le développement du composant final type Laboratoire sur Puce, les principes de détection aussi bien que les matériaux d'électrode qui vont être intégrés, ont été validés en utilisant un type de composant plus simple, qui a été réalisé grâce aux technologies de fabrication silicium et qui a été caractérisé par des procédures plus simples. Une puce sur silicium contenant un microsystème électrochimique intégrant trois électrodes a été mis en place. Une fois validés, les matériaux de détection et les configurations choisis précédemment ont été utilisés pour la fabrication des composants Laboratoire sur Puce. Les composants Laboratoire sur Puce ont été ensuite utilisés pour des tests biologiques afin de détecter les herbicides d'intérêt. Une attention spéciale a été placée sur le suivi de O2 comme indicateur de la présence d'herbicide, étant donné que cet élément est le plus représentatif de modifications de l'activité métabolique. Un effet d'inhibition sur la photosynthèse, dépendant de la concentration de l'herbicide a été démontré. La détection de l'herbicide a été réalisée avec une grande sensibilité et sur une gamme couvrant la limite de concentration maximale acceptable imposé par le gouvernement canadien. / Water quality assessment has attracted wide attention during the last decades in order to find ways to control contamination of water bodies induced, in a big part, by agricultural and industrial activities. Although conventional techniques, such as chromatography are highly accurate and sensitive tools, increasing interest has been placed lately to powerful alternative techniques that can be used on field, are cost-effective and offer the possibility of conducting rapid analysis. The present work was therefore dedicated to the development of a lab-on-chip device for water toxicity analysis. It consists in a portable system for on-site detection and aims at offering the possibility of conducting double complementary detection: optical and electrochemical. Since the optical sensor is already validated, this study focused on the implementation of the algal-based, electrochemical biosensor for detection water contaminants. The basic detection principle consists in monitoring disturbances in metabolic activities of algae induced by the presence of the herbicides. Algal response is different for each herbicide concentration in the examined sample. The two selected herbicides affect algal photosynthetic activity and consequently induce modifications in the quantity of electroactive species, O2, H2O2 and H3O+/OH- ions related to pH, produced by algae. Prior to the development of the final lab-on-chip device, the detection principle as well as the electrode materials that were going to be integrated were validated using a simpler device that was implemented using a silicon-based fabrication technology and was characterized using simpler procedures. A silicon chip containing the integrated three-electrode electrochemical microsystem was fabricated. The performance of the microsystem was evaluated through electrochemical characterization and calibration was performed. Once validated, the aforementioned materials and configurations were used for the fabrication of the lab-on-chip devices. The lab-on-chip devices were further used in bioassays to detect the herbicides of interest. Special emphasis was placed on O2 monitoring as indicator of the presence of herbicide, as it is the element the most representative of variations in metabolic activities. A concentration-dependent inhibition effect of the herbicide on photosynthesis was demonstrated. Herbicide detection was achieved with a greater sensitivity and a range covering the limit of maximum acceptable concentration imposed by Canadian government.

ETS1 est un facteur de transcription (FT) spécifique transposé dans les leucémies aigües. Le rôle essentiel d'ETS1 a été décrit au cours de l'hématopoïèse, plus particulièrement dans la différenciation lymphocytaire T. Son expression temporelle coordonnée participe au contrôle des transitions du stade double négatif (DN) CD4-/CD8- au stade double positif (DP) CD4+/CD8+jusqu'au stade simple positif (SP) CD4+ ou CD8+. Au cours de l'ontogenèse T, ETS1 transactive notamment l'expression des chaînes β et α du récepteur des cellules T (TCR). Nous avons criblé à grande échelle les cibles d'ETS1 aux stades DN et DP en ChIP-Seq, ainsi que desmarques histone et de l'ARN polymérase II (Pol II). Afin de faciliter nos analyses bioinformatiques, nous avons développé deux logiciels, CoCAS et AmaMineReg, qui permettent d'identifier plus facilement les cibles à partir de données brutes et de discriminer les vrais des faux positifs. Nous avons trouvé 5900 cibles en DN et 3400 en DP, principalement intergéniques dont 2000 sont communes, non caractérisées et correspondent aux gènes induits par la réponse immédiate à la signalisation TCR. Parmi les cibles différentiellement exprimées entre les deux stades, ETS1 active les gènes thymus-spécifiques et réprime les gènes hématopoïétiques non T spécifiques,en fonction de la co-occurrence avec le motif RUNX1. Nous avons également caractérisé très clairement le site de fixation en conditions natives, qui se révèle être CTTCCT.De plus, ETS1 co-localise avec des marques chromatines permissives aux régions inter- et intragéniques,caractérisées par un contenu GC, densité de motifs de fixation de FT (SFFT) et conservation inter-espèces accrus. / ETS1 is a specific transcription factor (TF) transposed in acute leukemias. key role of ETS1 wasdescribed during hematopoiesis, especially in T lymphocyte differentiation. Its temporal expression participates in the coordinated control of phase transitions from the CD4-/CD8-double negative (DN) stage to CD4+/CD8+ double positive (DP) up to CD4 or CD8 single positivestage (SP). During ontogenesis T ETS1 notably transactivates the expression of the alpha and beta chains of the T-Cell receptor (TCR). We performed genome-wide screening of ETS1 at both DN and DP stages via ChIP-Seq, as well as histone hallmarks and RNA polymerase II (PolII). To facilitate computational analysis we developed two new software suites, and COCASAmaMineReg, which allow easier identification of targets from raw data and to discriminate between true and false positives. We found 5900 targets in 3400 in DN and DP, mostly intergenic, out of which 2000 are common, and correspond to uncharacterized genes induced bythe immediate response to TCR signaling. Among targets differentially expressed between thetwo stages, Ets1 activates thymus-specific genes and represses non T-specific haematopoietic genes depending on the co-occurrence with the RUNX1 motif. We also very clearly characterized the binding site in native conditions, which proved to be CTTCCT. Furthermore, Ets1 colocalizes with permissive chromatin marks in inter-and intra-genic regions, characterized byincreased GC content, TF binding motifs (TFBS) density as well as inter-species conservation

In this report the two-tone PLL circuit intended for on-chip test of RF blocks is presented. The primary application is the third order intermodulation test (TOI), vital for RF front-ends. If the spectral analysis can also be completed by DSP available on the chip or on board, it provides a built in self-test (BiST) which can replace costly test instrumentation (ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect while keeping the two oscillation frequencies close. Also by careful design the possible intermodulation distortion of the two-tone stimulus can be avoided. The two-tone PLL has been designed and verified at the system level using Verilog-A models in Cadence TM. Besides, two building blocks of the PLL were implemented at the circuit level in 90nm CMOS technology. The obtained results are promising in terms of a practical two-tone BiST implementation.

Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today’s surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.

The advent of multi-core processors, particularly with projections that numbers of cores will continue to increase, has focused attention on parallel programming. It is widely recognized that current programming techniques, including those that are used for scientific parallel programming, will not allow the easy formulation of general purpose applications. An area which is receiving interest is the use of programming styles which do not have side-effects. Previous work on parallel functional programming demonstrated the potential of this to permit the easy exploitation of parallelism. This thesis investigates a dynamic load balancing system for shared memory Chip Multiprocessors. This system is based on a parallel computing model called SLAM (Spreading Load with Active Messages), which makes use of functional language evaluation techniques. A novel hardware/software mechanism for exploiting fine grain parallelism is presented. This mechanism comprises a runtime system which performs dynamic scheduling and synchronization automatically when executing parallel applications. Additionally the interface for using this mechanism is provided in the form of an API. The proposed system is evaluated using cycle-level models and multithreaded applications running in a full system simulation environment.

Recently, there is great interest in achieving higher-level integration, higher data rates, and reduced overall costs. At millimeter-wave (mm-wave) bands, the wavelength is small enough to realize an antenna-on-chip (AoC), which is an ideal solution for high compactness and lower costs. However, the main drawback of AoC is the low resistivity (10 Ω-cm) Si substrate used in the standard CMOS technology, which absorbs most radio-frequency (RF) power that was supposed to be radiated by the on-chip antenna. Moreover, due to the high relative permittivity (11.9) and relatively large electrical thickness of the Si, higher order surface wave modes get excited, which further degrade the antenna radiation performance. In order to alleviate the above-mentioned issues with the low gain of AoC, a combination of an artificial magnetic conductor (AMC) surface, a high dielectric constant superstrate, and a Fresnel lens is presented in this work. The AMC is realized in standard CMOS technology along with the AoC, whereas the superstrate and lens are part of a smart packaging solution. The AMC surface can change wave propagation characteristics at the operating frequency to achieve in-phase reflection, resulting in gain enhancement by reducing the loss in the substrate. The high dielectric constant superstrate behaves as an impedance transformer between the Si substrate and air, thus enhancing the coupling to air. Finally, the Fresnel lens enhances the gain by focusing the electromagnetic (EM) radiation beam at the boresight. For AoC realization, a standard 0.18 μm CMOS process was utilized. A coplanar waveguide (CPW) fed monopole on-chip antenna at 71 GHz, along with the corresponding driving circuit, was designed and fabricated. The AMC enhances the gain by 3 dB. Since the chip needs to be packaged anyways, in this work, we optimize the package to provide further gain enhancement. This smart package, comprising a superstrate and a Fresnel lens, provides a gain enhancement of 16 dB. The overall combination of the optimized AMC surface, superstrate layer, and lens package can provide a gain enhancement of around 19 dB. Furthermore, the package has been realized through additive manufacturing techniques that ensure lower costs for the overall system.