In this thesis, we compare the energy efficiency of various strategies of mobile computation offloading over stochastic transmission channels where the task completion time is subject to a latency constraint. In the proposed methods, finite-state Markov chains are used to model the wireless channels between the mobile devices and the remote servers. We analyze the mechanisms of efficient mobile computation offloading under both soft and hard latency constraints. For the case of soft latency constraint, the task completion could miss the deadline below a specified probability threshold. On the other hand, under a hard deadline constraint, the task execution result must be available at the mobile device before the deadline. In order to make sure the task completes before the hard deadline, the hard deadline constraint approach requires concurrent execution in both local and cloud in specific circumstances. The closed-form solutions are often obtained using the broad Markov processes. The GE (Gilbert-Elliott) model is a more efficient method for demonstrating how the Markov chain’s structure can be used to compute the best offload initiation (Hekmati et al., 2019a).The effectiveness of the algorithms is studied under various deadline constraints and offloading methods. In this thesis, six algorithms are assessed in various scenarios. 1) Single user optimal (Zhang et al., 2013), 2) LARAC (Lagrangian Relaxation Based Aggregated Cost) (Zhang et al., 2014), 3) OnOpt (Online Optimal) algorithm (Hekmati et al., 2019a), 4) Water-Filling With Equilibrium (WF-Equ), 5) Water-Filling With Exponentiation (WFExp) (Teymoori et al., 2021), 6) MultiOPT (Multi-Decision Online Optimal). The experiment demonstrates that the studied algorithms perform dramatically different in the same setting. The various types of deadline restrictions also affect how efficiently the algorithms use energy. The experiment also highlights the trade-off between computational complexities and mobile energy savings (Teymoori et al., 2021).

O aumento da popularidade da Internet e a criação de novos meios de transmissão estimulam um explosivo crescimento da taxa de transmissão de dados sobre a Internet. Assim, o processamento TCP/IP baseado em software torna-se um gargalo por não processar os pacotes na velocidade das linhas de transmissão, em especial os pacotes da camada de transporte. Conseqüentemente, surge a necessidade de implementação em hardware do processamento TCP/IP, o que traria vantagens como aceleração do processamento do fluxo de dados. Neste sentido, este trabalho apresenta a arquitetura do iNetCore, descrita em VHDL, para processamento dos protocolos das camadas de rede e transporte em hardware. Duas implementações desta arquitetura foram elaboradas, buscando explorar o espaço de projeto e analisar os resultados obtidos na síntese para a tecnologia ASIC e FPGA, e o desempenho no processamento de pacotes. Uma arquitetura HW/SW contendo o iNetCore foi prototipada sobre a placa Virtex- II Pro Development System. Em conjunto com essa arquitetura, foi implementada uma interface de comunicação com o barramento OPB, tornando possível a implementação de softwares da camada de aplicação que queiram usar a pilha TCP/IP desenvolvida em hardware. Por fim, foram efetuados experimentos para avaliar o desempenho da arquitetura HW/SW no processamento de segmentos TCP. A arquitetura HW/SW em conjunto com o iNetCore alcançou um throughput de até 1,45 Gbps, possibilitando o uso da arquitetura para processamento de pacotes TCP/IP na plenitude de banda disponíveis em redes gigabit. / The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the TCP/IP processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the TCP/IP processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware TCP/IP stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the TCP segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the TCP/IP packets processing. It proves its potential to use available bandwidth in gigabit networks.

The ambulance offload delay problem is a well-known result of overcrowding and congestion in emergency departments. Offload delay refers to the situation where area hospitals are unable to accept patients from regional ambulances in a timely manner due to lack of staff and bed capacity. The problem of offload delays is not a simple issue to resolve and has caused severe problems to the emergency medical services (EMS) providers, emergency department (ED) staff, and most importantly patients that are transferred to hospitals by ambulance. Except for several reports on the problem, not much research has been done on the subject. Almost all research to date has focused on either EMS or ED planning and operation and as far as we are aware there are no models which have considered the coordination of these units. We propose an analytical model which will allow us to analyze and explore the ambulance offload delay problem. We use queuing theory to construct a system representing the interaction of EMS and ED, and model the behavior of the system as a continuous time Markov chain. The matrix geometric method will be used to numerically compute various system performance measures under different conditions. We analyze the effect of adding more emergency beds in the ED, adding more ambulances, and reducing the ED patient length of stay, on various system performance measures such as the average number of ambulances in offload delay, average time in offload delay, and ambulance and bed utilization. We will show that adding more beds to the ED or reducing ED patient length of stay will have a positive impact on system performance and in particular will decrease the average number of ambulances experiencing offload delay and the average time in offload delay. Also, it will be shown that increasing the number of ambulances will have a negative impact on offload delays and increases the average number of ambulances in offload delay. However, other system performance measures are improved by adding more ambulances to the system. Finally, we will show the tradeoffs between adding more emergency beds, adding more ambulances, and reducing ED patient length of stay. We conclude that the hospital is the bottleneck in the system and in order to reduce ambulance offload delays, either hospital capacity has to be increased or ED patient length of stay is to be reduced.

The ambulance offload delay problem is a well-known result of overcrowding and congestion in emergency departments. Offload delay refers to the situation where area hospitals are unable to accept patients from regional ambulances in a timely manner due to lack of staff and bed capacity. The problem of offload delays is not a simple issue to resolve and has caused severe problems to the emergency medical services (EMS) providers, emergency department (ED) staff, and most importantly patients that are transferred to hospitals by ambulance. Except for several reports on the problem, not much research has been done on the subject. Almost all research to date has focused on either EMS or ED planning and operation and as far as we are aware there are no models which have considered the coordination of these units. We propose an analytical model which will allow us to analyze and explore the ambulance offload delay problem. We use queuing theory to construct a system representing the interaction of EMS and ED, and model the behavior of the system as a continuous time Markov chain. The matrix geometric method will be used to numerically compute various system performance measures under different conditions. We analyze the effect of adding more emergency beds in the ED, adding more ambulances, and reducing the ED patient length of stay, on various system performance measures such as the average number of ambulances in offload delay, average time in offload delay, and ambulance and bed utilization. We will show that adding more beds to the ED or reducing ED patient length of stay will have a positive impact on system performance and in particular will decrease the average number of ambulances experiencing offload delay and the average time in offload delay. Also, it will be shown that increasing the number of ambulances will have a negative impact on offload delays and increases the average number of ambulances in offload delay. However, other system performance measures are improved by adding more ambulances to the system. Finally, we will show the tradeoffs between adding more emergency beds, adding more ambulances, and reducing ED patient length of stay. We conclude that the hospital is the bottleneck in the system and in order to reduce ambulance offload delays, either hospital capacity has to be increased or ED patient length of stay is to be reduced.

<p>Advances in mobile hardware and operating systems have made mobile a first-class development platform. Activities such as web browsing, casual game play, media playback, and document reading are now as common on mobile devices as on full-sized desktop systems. However, developers are still constrained by the inherent resource limitations of mobile devices. Unlike desktop systems, mobile devices must sacrifice performance to accomodate smaller form factors and battery-backed operation. Opportunistic offloading of computation from a mobile device to remote server infrastructure (i.e., "code offload") offers a promising way to overcome these constraints and to expand the set of applications</p><p>(i.e., "apps") that can run on devices.</p><p>Deciding to offload requires a careful consideration of the costs and benefits of a range of possible program partitions. This cost-benefit analysis depends on external factors, such as network conditions and the resources availability, as well as internal app properties, such as component dependencies, data representations, and code complexity. Thus, benefiting from offload requires some assistance from developers, but requiring developers to adopt arcane or unnatural programming models will hinder adoption of regardless of the potential benefits.</p><p>In this dissertation we characterize two frameworks that reduce the amount of developer effort required to improve the performance of mobile apps through code offload. The first, MAUI, is designed for computationally intensive general-purpose apps such as speech</p><p>and facial recognition. The second, Kahawai, is designed for graphics-intensive apps like fast-action video games.</p><p>MAUI continuously monitors the device, network, and app, and uses its measurements to compute an energy-efficient program partition. MAUI reduces the burden on developers by taking advantage of core features of the managed code environments common to mobile</p><p>platforms: code portability, serialization, reflection, and type safety. These features allows MAUI to automatically instrument and potentially offload methods that the developer has tagged as suitable for offload. MAUI is particularly effective on applications composed by operations whose computational cost is large compared to the transfer cost of their input parameters and their output results.</p><p>Kahawai is designed for graphics-intensive apps such as console-style games and takes advantage of two features of today's mobile gaming platforms: capable mobile GPUs and reusable game engines. Even though today's mobile devices cannot duplicate the sophisticated graphical detail provided by gaming consoles and high-end desktop GPUs, devices have seen rapid improvements in their GPU processing capabilities. Kahawai leverages a device's GPU to provide collaborative rendering. Collaborative rendering relies on a mobile GPU to generate low-fidelity output, which when combined with server-side GPU output allows a mobile device to display a high-fidelity result. The benefits of collaborative rendering are substantial: mobile clients can experience high-quality graphical output using relatively little bandwidth. Fortunately, because most modern games are built on top of reusable game engines, developers only have to identify the sources of non-determinism</p><p>in the game logic to take advantage collaborative rendering.</p><p>Together, MAUI and Kahawai demonstrate that code offload can provide substantial benefits for mobile apps without overburdening app developers.</p> / Dissertation

O aumento da popularidade da Internet e a criação de novos meios de transmissão estimulam um explosivo crescimento da taxa de transmissão de dados sobre a Internet. Assim, o processamento TCP/IP baseado em software torna-se um gargalo por não processar os pacotes na velocidade das linhas de transmissão, em especial os pacotes da camada de transporte. Conseqüentemente, surge a necessidade de implementação em hardware do processamento TCP/IP, o que traria vantagens como aceleração do processamento do fluxo de dados. Neste sentido, este trabalho apresenta a arquitetura do iNetCore, descrita em VHDL, para processamento dos protocolos das camadas de rede e transporte em hardware. Duas implementações desta arquitetura foram elaboradas, buscando explorar o espaço de projeto e analisar os resultados obtidos na síntese para a tecnologia ASIC e FPGA, e o desempenho no processamento de pacotes. Uma arquitetura HW/SW contendo o iNetCore foi prototipada sobre a placa Virtex- II Pro Development System. Em conjunto com essa arquitetura, foi implementada uma interface de comunicação com o barramento OPB, tornando possível a implementação de softwares da camada de aplicação que queiram usar a pilha TCP/IP desenvolvida em hardware. Por fim, foram efetuados experimentos para avaliar o desempenho da arquitetura HW/SW no processamento de segmentos TCP. A arquitetura HW/SW em conjunto com o iNetCore alcançou um throughput de até 1,45 Gbps, possibilitando o uso da arquitetura para processamento de pacotes TCP/IP na plenitude de banda disponíveis em redes gigabit. / The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the TCP/IP processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the TCP/IP processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware TCP/IP stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the TCP segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the TCP/IP packets processing. It proves its potential to use available bandwidth in gigabit networks.

O aumento da popularidade da Internet e a criação de novos meios de transmissão estimulam um explosivo crescimento da taxa de transmissão de dados sobre a Internet. Assim, o processamento TCP/IP baseado em software torna-se um gargalo por não processar os pacotes na velocidade das linhas de transmissão, em especial os pacotes da camada de transporte. Conseqüentemente, surge a necessidade de implementação em hardware do processamento TCP/IP, o que traria vantagens como aceleração do processamento do fluxo de dados. Neste sentido, este trabalho apresenta a arquitetura do iNetCore, descrita em VHDL, para processamento dos protocolos das camadas de rede e transporte em hardware. Duas implementações desta arquitetura foram elaboradas, buscando explorar o espaço de projeto e analisar os resultados obtidos na síntese para a tecnologia ASIC e FPGA, e o desempenho no processamento de pacotes. Uma arquitetura HW/SW contendo o iNetCore foi prototipada sobre a placa Virtex- II Pro Development System. Em conjunto com essa arquitetura, foi implementada uma interface de comunicação com o barramento OPB, tornando possível a implementação de softwares da camada de aplicação que queiram usar a pilha TCP/IP desenvolvida em hardware. Por fim, foram efetuados experimentos para avaliar o desempenho da arquitetura HW/SW no processamento de segmentos TCP. A arquitetura HW/SW em conjunto com o iNetCore alcançou um throughput de até 1,45 Gbps, possibilitando o uso da arquitetura para processamento de pacotes TCP/IP na plenitude de banda disponíveis em redes gigabit. / The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the TCP/IP processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the TCP/IP processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware TCP/IP stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the TCP segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the TCP/IP packets processing. It proves its potential to use available bandwidth in gigabit networks.

The primary research objective of this dissertation is to demonstrate that the effects of communication protocol stack offload (CPSO) on application execution time can be attributed to the following two complementary sources. First, the application-specific computation may be executed concurrently with the asynchronous communication performed by the communication protocol stack offload engine. Second, the protocol stack processing can be accelerated or decelerated by the offload engine. These two types of performance effects can be quantified with the use of the degree of overlapping Do and degree of acceleration Daccs. The composite communication speedup metrics S_comm(Do, Daccs) can be used in order to quantify the combined effects of the protocol stack offload. This dissertation thesis is validated empirically. The degree of overlapping Do, the degree of acceleration Daccs, and the communication speedup Scomm characteristic of the system configurations under test are derived in the course of experiments performed for the system configurations of interest. It is shown that the proposed metrics adequately describe the effects of the protocol stack offload on the application execution time. Additionally, a set of analytical models of the networking subsystem of a PC-based cluster node is developed. As a result of the modeling, the metrics Do, Daccs, and Scomm are obtained. The models are evaluated as to their complexity and precision by comparing the modeling results with the measured values of Do, Daccs, and Scomm. The primary contributions of this dissertation research are as follows. First, the metric Daccs and Scomm are introduced in order to complement the Do metric in its use for evaluation of the effects of optimizations in the networking subsystem on parallel performance in clusters. The metrics are shown to adequately describe CPSO performance effects. Second, a method for assessing performance effects of CPSO scenarios on application performance is developed and presented. Third, a set of analytical models of cluster node networking subsystems with CPSO capability is developed and characterised as to their complexity and precision of the prediction of the Do and Daccs metrics.

Cette thèse présente une solution pour améliorer la mobilité des réseaux, dans le cadre de communications véhiculaires ainsi que pour la distribution de contenu. Les solutions actuelles pour les communications véhiculaires (c'est-à-dire lorsqu'un réseau est mobile) reposent sur la mise en place de tunnels, permettant également d'utiliser simultanément les différentes interfaces disponibles sur le véhicule (multi-homing). Même avec des tunnels, ces solutions ne sont pas en mesure d'équilibrer le trafic sur les interfaces réseau disponibles, elles ne parviennent pas à tirer partie du multi-homing. De plus, certaines des solutions existantes pour la mobilité de réseau cachent la mobilité aux hôtes connectés au routeur mobile. De fait, cela empêche les hôtes de participer aux décisions relatives au multi-homing, telles que le choix de l'interface réseau à utiliser, ce qui est pourtant utile pour réaliser du routage à moindre coût. Dans cette thèse, nous proposons de combiner un protocole de mobilité réseau (tel que NEMO) avec le protocole de TCP-multivoies (MPTCP), ce qui permet aux nœuds hôtes de participer à la mobilité et au multi-homing. Cette nouvelle combinaison améliore significativement le routage et l'encapsulation de paquets causée par les tunnels. En outre, cela augmente le débit, la tolérance de panne, le temps d'aller-retour et réduit le délai de transmission. La deuxième contribution de ce travail propose une solution de continuité de session pour la distribution de contenu dans les réseaux 5G. Dans le réseau 5G, les équipements d'accès IP seront au plus proche des nœuds terminaux afin d'améliorer l'expérience utilisateur et de réduire la charge de trafic dans le réseau central. Le fait est qu'à un instant donné un terminal ne peut être raccordé qu'à une seule passerelle (SGW/PGW) à la fois. Et comme la passerelle change lors de la mobilité, les sessions en cours seront rompues, impactant les applications temps réelle, le streaming vidéo, les jeux, etc. Pour cela, la thèse présente une solution de continuité de session avec l'aide de TCP-multivoie en bénéficiant du fait que les serveurs de contenu sont stationnaires. / This thesis presents a solution for boosting network mobility in the context of vehicular communications and content distribution in fixed network. Existing solutions for vehicular communications (i.e., network mobility), relies on tunneling in order to use multiple available interfaces on a vehicle. Even with tunnels, these solutions are unable to balance the traffic over available network interfaces thus do not reach the goal to provide optimum multi-homing benefits. Moreover, some of the existing solutions for network mobility, hide the mobility from the hosts connected to the mobile router. This in result inhibits the host nodes from participating in multi-homing related decisions such as interface selection which can be helpful in performing least cost routing. In this thesis, we propose to combine network mobility protocol with MPTCP which enables the host nodes to participate in mobility and multi-homing. This novel combination significantly improves routing and tunneling packet overhead. Moreover it increases throughput, fault tolerance, round-trip time and reduces transmission delay. The second contribution of this work is providing a solution for session continuity in context of content distribution in 5G networks. In 5G network, the IP edges will be closer to the host nodes in order to improve the user experience and reduce traffic load in the core network. The fact that a host can only be connected to a single gateway (SGW/PGW) at a time, would break the ongoing sessions for real time applications like video streaming or gaming during an occurrence of mobility event requiring gateway relocation. The thesis presents the solution for session continuity with the help of multipath TCP by benefiting from the fact that the content servers are stationary.

Although healthcare operations management has been an active and popular research direction over the past few years, there is a lack of formal quantitative models to analyze the ambulance o oad delay problem. O oad delays occur when an ambulance arriving at a hospital Emergency Department (ED) is forced to remain in front of the ED until a bed is available for the patient. Thus, the ambulance and the paramedic team are responsible to care for the patient until a bed becomes available inside the ED. But it is not as simple as waiting for a bed, as EDs also admit patients based on acuity levels. While the main cause of this problem is the lack of capacity to treat patients inside the EDs, Emergency Medical Services (EMS) coverage and availability are signi cantly a ected. In this thesis, we develop three network queueing models to analyze the o oad delay problem. In order to capture the main cause of those delays, we construct queueing network models that include both EMS and EDs. In addition, we consider patients arriving to the EDs by themselves (walk-in patients) since they consume ED capacity as well. In the rst model, ED capacity is modeled as the combination of bed, nurse, and doctor. If a patient with higher acuity level arrives to the ED, the current patient's service is interrupted. Thus, the service discipline at the EDs is preemptive resume. We also assume that the time the ambulance needs to reach the patient, upload him into the ambulance, and transfer him to the ED (transit time) is negligible. We develop e cient algorithms to construct the model Markov chain and solve for its steady state probability distribution using Matrix Analytic Methods. Moreover, we derive di erent performance measures to evaluate the system performance under di erent settings in terms of the number of beds at each ED, Length Of Stay (LOS) of patients at an ED, and the number of ambulances available to serve a region. Although capacity limitations and increasing demand are the main drivers for this problem, our computational analysis show that ambulance dispatching decisions have a substantial impact on the total o oad delays incurred. In the second model, the number of beds at each ED is used to model the service capacity. As a result of this modeling approach, the service discipline of patients is assumed to be nonpreemptive priority. We also assume that transit times of ambulances are negligible. To analyze the queueing network, we develop a novel algorithm to construct the system Markov chain by de ning a layer for each ED in a region. We combine the Markov chain layers based on the fact that regional EDs are only connected by the number of available ambulances to serve the region. Using Matrix Analytic Methods, we nd the limiting probabilities and use the results to derive di erent system performance measures. Since each ED's patients are included in the model simultaneously, we solve only for small instances with our current computational resources. In the third model, we decompose the regional network into multiple single EDs. We also assume that patients arriving by ambulances have higher nonpreemptive priority discipline over walk-in patients. Unlike the rst two models, we assume that transit times of ambulances are exponentially distributed. To analyze the decomposed queueing network performance, we construct a Markov chain and solve for its limiting probabilities using Matrix Analytic Methods. While the main objective for the rst two models is performance evaluation, in this model we optimize the steady state dispatching decisions for ambulance patients. To achieve this goal, we develop an approximation scheme for the expected o oad delays and expected waiting times of patients. Computational analysis conducted suggest that larger EDs should be loaded more heavily in order to keep the total o oad delays at minimal levels.