Techn. Universiẗat, Diss., 2005--Darmstadt.

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 76-84).

Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. / Includes bibliographical references.

Made available in DSpace on 2014-12-17T15:47:00Z (GMT). No. of bitstreams: 1 SilvioRFA_TESE.pdf: 5797455 bytes, checksum: 65da3be6db5be8c8185888e31c1f294c (MD5) Previous issue date: 2012-03-30 / It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it / Aposta-se na pr?xima gera??o de computadores como sendo de arquitetura com m?ltiplos processadores e/ou processadores com v?rios n?cleos. Neste sentido h? desafios relacionados aos mecanismos de interconex?o, frequ?ncia de opera??o, ?rea ocupada em chip, pot?ncia dissipada, programabilidade e desempenho. O mecanismo de interconex?o e comunica??o considerado ideal para esse tipo de arquitetura s?o as redes em chip, pela escalabilidade, paralelismo intr?nseco e reusabilidade. A comunica??o nas redes em chip ? realizada atrav?s da transmiss?o de pacotes que carregam dados e instru??es que representam requisi??es e respostas entre os elementos processadores interligados pela rede. A transmiss?o desses pacotes acontece como em um pipeline entre os roteadores da rede, da origem at? o destino da comunica??o, permitindo inclusive comunica??es simult?neas entre pares de origem e destinos diferentes. Partindo desse fato, prop?ese transformar toda a infraestrutura de comunica??o de uma rede em chip, aproveitando os mecanismos de roteamento, arbitragem e memoriza??o em um sistema de processamento paralelo de alto desempenho. Nessa proposta os pacotes s?o formados por instru??es e dados que representam as aplica??es, os quais s?o executados nos roteadores enquanto s?o transmitidos, aproveitando o pipeline das transmiss?es e a comunica??o paralela. Em contrapartida, n?o s?o utilizados processadores tradicionais, mas apenas n?cleos simples que controlam o acesso a mem?ria. Uma implementa??o dessa ideia ? a arquitetura intitulada IPNoSys (Integrated Processing NoC System), que conta com um modelo de programa??o pr?prio e um algoritmo de roteamento que garante a execu??o de todas as instru??es presentes nos pacotes, prevenindo situa??es de deadlock, livelock e starvation. Essa arquitetura apresenta mecanismos de entrada e sa?da, interrup??o e suporte ao sistema operacional. Como prova de conceito foi desenvolvido um ambiente de programa??o e simula??o para esta arquitetura em SystemC, o qual permite a configura??o de v?rios par?metros da arquitetura e obten??o dos resultados para avalia??o da mesma

Made available in DSpace on 2014-12-17T15:47:45Z (GMT). No. of bitstreams: 1 SilvioRFA.pdf: 3522539 bytes, checksum: 0e7ac6eda46a29d5f5968d779986fb03 (MD5) Previous issue date: 2008-04-11 / The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform / O aumento na capacidade de integra??o de transistores permitiu o desenvolvimento de sistemas completos, com in?meros componentes, dentro de um ?nico chip, s?o os chamados SoCs (System-on-Chip). No entanto, o subsistema de interconex?o utilizado pode limitar a escalabilidade dos SoCs, como os barramentos, ou ser uma solu??o ad hoc, como a hierarquia de barramentos. Desse modo, a solu??o ideal para interconex?o no SoCs s?o as redes em chip ou NoCs (Network-on-Chip). As NoCs permitem m?ltiplas conex?o ponto-a-ponto entre os componente e podem ser reusadas em projetos diversos. Entretanto, o uso de NoCs pode representar o aumento na complexidade do projeto do sistema, da ?rea em chip e/ou pot?ncia dissipada. Dessa forma, ? necess?rio ampliar o horizonte de utiliza??o dos sistemas ou quebrar o paradigma do seu desenvolvimento. Assim, ? proposto um sistema baseado em uma NoC, onde as aplica??es s?o descritas em forma de pacotes e executadas de roteador em roteador durante o percurso entre origem e destino dos pacotes, sem a necessidade do uso de processadores convencionais. Para permitir a execu??o de aplica??es, independente do n?mero de instru??es e das dimens?es da rede, foi desenvolvido o algoritmo spiral complement, que permite re-rotear pacotes at? que todas as instru??es contidas nele sejam executadas. Portanto, o objetivo desse trabalho foi estudar a viabilidade do desenvolvimento de tal sistema, denominado sistema IPNoSys. Nesse estudo, foi desenvolvida em SystemC, com precis?o de ciclo, uma ferramenta para simula??o do sistema, a qual permite executar aplica??es implementadas na linguagem de descri??o de pacotes, tamb?m desenvolvida para esse fim. Atrav?s da ferramenta podem ser obtidos diversos resultados que permitem avaliar o funcionamento e desempenho do sistema. A metodologia empregada para descri??o das aplica??es corresponde, a priori, em obter o grafo de fluxo de dados da aplica??o em alto n?vel, e desse grafo descrev?-la em um ou mais pacotes. Utilizando essa metodologia, foram realizados tr?s estudos de casos: contador, DCT-2D e adi??o de ponto flutuante. O contador foi usado para avaliar a capacidade do sistema em tratar situa??es de deadlock e executar aplica??es em paralelo. A DCT-2D foi utilizada para realizar compara??es com a plataforma STORM. E, finalmente, a adi??o de ponto flutuante teve como objetivo ser usada como rotina de tratamento de uma instru??o n?o implementada em hardware. Os resultados de simula??o apontam favoravelmente com rela??o ? viabilidade do desenvolvimento do sistema IPNoSys. Mostrando que ? poss?vel executar aplica??es em forma de pacotes, inclusive paralelamente, sem interrup??es provocadas por eventuais deadlocks, e ainda indicam maior efici?ncia do sistema IPNoSys a respeito do tempo de execu??o comparada a plataforma STORM

Made available in DSpace on 2014-12-17T15:47:50Z (GMT). No. of bitstreams: 1 BrunoCO.pdf: 708202 bytes, checksum: 3eb4368a0c268064bcd6ad892e1f2c0c (MD5) Previous issue date: 2009-05-22 / The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit, the most viable solution is the use of parallelism. Based on parallelism techniques and the progressive growth in the capacity of transistors integration in a single chip is the concept of MPSoCs (Multi-Processor System-on-Chip). MPSoCs will eventually become a cheaper and faster alternative to supercomputers and clusters, and applications developed for these high performance systems will migrate to computers equipped with MP-SoCs containing dozens to hundreds of computation cores. In particular, applications in the area of oil and natural gas exploration are also characterized by the high processing capacity required and would benefit greatly from these high performance systems. This work intends to evaluate a traditional and complex application of the oil and gas industry known as reservoir simulation, developing a solution with integrated computational systems in a single chip, with hundreds of functional unities. For this, as the STORM (MPSoC Directory-Based Platform) platform already has a shared memory model, a new distributed memory model were developed. Also a message passing library has been developed folowing MPI standard / O constante aumento da complexidade das aplica??es demanda um suporte de hardware computacionalmente mais poderoso. Com a aproxima??o do limite de velocidade dos processadores, a solu??o mais vi?vel ? o paralelismo. Baseado nisso e na crescente capacidade de integra??o de transistores em um ?nico chip surgiram os chamados MPSoCs (Multiprocessor System-on-Chip) que dever?o ser, em um futuro pr?ximo, uma alternativa mais r?pida e mais barata aos supercomputadores e clusters. Aplica??es tidas como destinadas exclusivamente a execu??o nesses sistemas de alto desempenho dever?o migrar para m?quinas equipadas com MPSoCs dotados de dezenas a centenas de n?cleos computacionais. Aplica??es na ?rea de explora??o de petr?leo e g?s natural tamb?m se caracterizam pela enorme capacidade de processamento requerida e dever?o se beneficiar desses novos sistemas de alto desempenho. Esse trabalho apresenta uma avalia??o de uma tradicional e complexa aplica??o da ind?stria de petr?leo e g?s natural, a simula??o de reservat?rios, sob a nova ?tica do desenvolvimento de sistemas computacionais integrados em um ?nico chip, dotados de dezenas a centenas de unidades funcionais. Para isso, um modelo de mem?ria distribu?da foi desenvolvido para a plataforma STORM (MPSoC Directory-Based Platform), que j? contava com um modelo de mem?ria compartilhada. Foi desenvolvida, ainda, uma biblioteca de troca de mensagens para esse modelo de mem?ria seguindo o padr?o MPI

Monitoring and controlling pH is of utmost importance in bioprocessing as it directly affects product yield and quality. Multiplexed experiments can be performed in nanobioreactors for optimisation of yield and cell heterogeneity in a relatively quick and inexpensive manner. In this thesis, a pH holographic sensor (holosensor) is miniaturised to 3.11 nL in volume and integrated into a PDMS-glass microfluidic chip for monitoring the growth of Lactobacillus casei Shirota. Although other established methods for monitoring cell cultures can be utilised, miniaturised holosensors enable real-time and non-consumptive monitoring of the bacterial cell culture growth medium. The 2-hydroxyethylmethacrylate (HEMA)-co-2-(trifluoromethyl) propenoic acid (TFMPA) holosensor was fabricated using an adapted technique from photolithography, coupled with the use of a polymerisation inhibitor to control the gel polymerisation with diameters not exceeding a standard deviation of 0.067. The hologram brightness was optimised to 1.05 ms integration time with 36X magnification using a low power (0.290 mW) 532 nm green continuous wave (CW) laser with a devised beam-offset technique. The holosensor was characterised with ionic strength balanced (9.50 mS/cm) McIIvaine pH buffers and a calibration curve plotted together with measured ionic strength, optical density at 600 nm (OD600) and pH. Correspondingly, RGB-xyY transformed values were plotted in the CIE 1931 chromaticity diagram. Later, a miniaturised 0.4φ HEMA-co-TFMPA holosensor and array was also demonstrated. Together with the 3.0φ holosensor, an accuracy parameter for the 0.4φ spot and array holosensors were calculated to be 99.08%, 99.38% and 97.77% respectively. Further work involved studying the issues associated with fabricating gels with unusually flat gel profiles. Other preliminary results suggested the alternative of utilising polymers as a holosensor substrate, together with a dye-free method for hologram fabrication, outlined the prospective possibility of a miniaturised holosensor integrated into a polymer microfluidic chip with the flexibility of hologram colour customisation for cell culture monitoring.

In eukaryotes, DNA is wrapped around a group of proteins termed histones that are required to precisely control gene expression during development. The amino acids of both the globular domains and unstructured tails of these histones can be modified by chemical moieties, such as methylation, acetylation and ubiquitination. The ‘histone code’ hypothesis proposes that specific combinations of these and other histone modifications contain transcriptional information, which guides the cell machinery to activate or repress gene expression in individual cell types. Chromatin immunoprecipitation (ChIP) experiments using undifferentiated stem cell populations have identified the genomic co-localisation of histone modifications reported to have opposing effects on transcription, which is known as bivalency. The human α-globin promoter, a well-established model for the study of transcriptional regulation, is bivalent in embryonic stem (ES) cells and this bivalency is resolved once the ES cells terminally differentiate (i.e. only activating or repressing marks remain). In a humanised mouse model, the deletion of a bone fide enhancer within the human α-globin locus results in heterogeneous expression patterns in primary erythroid cells. Notably, this correlates with an unresolved bivalent state at this promoter in terminally differentiated cells. Using this mouse model it is not feasible to ascertain whether the transcriptional heterogeneity observed in the cells lacking an α-globin enhancer is reflective of epigenetic heterogeneity (i.e. a mixed population of cells) rather than co-localisation of bivalent histone modifications within the same cells. Furthermore, the functional contribution of bivalency to development has yet to be described. To address these difficulties, I aimed to generate a fluorescent reporter system for human α-globin to facilitate the separation of transcriptionally heterogeneous erythroid cells. This model will provide material for ChIP studies on transcriptionally active and inactive populations to determine whether the epigenetic bivalency is reflective of a mixed cell population or true bivalency. In addition, I aimed to produce epigenetic editing tools to target bivalent promoters, which in combination with in vitro differentiation assays would provide an interesting framework to test the function of bivalency during development. In this study, I extensively tested gene-editing strategies for generating a fluorescent reporter knock-in in humanised mouse ES cells. I validated the suitability of humanised mouse ES cell lines for gene targeting studies and optimised a robust in vitro differentiation protocol for studying erythropoiesis. I utilised both recombineering and CRISPR/Cas9 gene editing tools in tandem with PiggyBac transposon technology, to knock-in the reporter gene. I made significant steps in gene targeting and successfully inserted the reporter downstream of the α-globin gene. I also generated a cloning system to express site-specific DNA-binding domains (TALEs) fused to epigenetic regulators with the aim to resolve bivalent histone modifications in vitro. From preliminary tests using these fusion proteins targeting Nrp1, a bivalent promoter in mES cells, I observed mild but significant changes in gene expression although histone modifications were unchanged. The various tools generated and tested in this study provide a solid foundation for future development of genetic and epigenetic editing at the human α-globin and other bivalent loci.

abstract: Filtration for microfluidic sample-collection devices is desirable for sample selection, concentration, preprocessing, and downstream manipulation, but microfabricating the required sub-micrometer filtration structure is an elaborate process. This thesis presents a simple method to fabricate polydimethylsiloxane (PDMS) devices with an integrated membrane filter that will sample, lyse, and extract the DNA from microorganisms in aqueous environments. An off-the-shelf membrane filter disc was embedded in a PDMS layer and sequentially bound with other PDMS channel layers. No leakage was observed during filtration. This device was validated by concentrating a large amount of cyanobacterium Synechocystis in simulated sample water with consistent performance across devices. After accumulating sufficient biomass on the filter, a sequential electrochemical lysing process was performed by applying 5VDC across the filter. This device was further evaluated by delivering several samples of differing concentrations of cyanobacterium Synechocystis then quantifying the DNA using real-time PCR. Lastly, an environmental sample was run through the device and the amount of photosynthetic microorganisms present in the water was determined. The major breakthroughs in this design are low energy demand, cheap materials, simple design, straightforward fabrication, and robust performance, together enabling wide-utility of similar chip-based devices for field-deployable operations in environmental micro-biotechnology. / Dissertation/Thesis / Additional Paper / M.S. Civil and Environmental Engineering 2011

Les progrès dans le domaine des semi-conducteurs ont permis la miniaturisation des puces et l’extension considérable de leurs capacités de calcul et de mémorisation. Cela s’est accompagné d’un accroissement très important du volume des données échangées à l’intérieur de ces puces, limitant les performances au débit de données dans la puce. Ainsi, les concepteurs ont proposé le réseau sur puce (ou NoC : Network-on-Chip) afin de répondre à ces besoins. Cependant, l’accroissement du trafic permis par ce réseau se traduit par une consommation énergétique plus importante engendrant une hausse de la température et une diminution de la fiabilité de la puce. L’élaboration de techniques d’optimisation de l’énergie du NoC est alors nécessaire. La première partie de cette thèse est consacrée à l’étude de la modélisation des NoCs afin d’estimer leur consommation et d’identifier les composants les plus consommateurs. Ainsi, la première contribution de cette thèse a été d’améliorer la modélisation du NoC en modifiant le modèle d’interconnexions d’un simulateur de NoC existant (Noxim), pour le rendre bit-près (Noxim-XT), et ainsi permettre au simulateur d’incorporer un modèle d’interconnexions considérant les effets du crosstalk, phénomène physique faisant varier leur consommation d’énergie. La seconde partie de la thèse traite de l’optimisation de la consommation d’énergie du NoC. Ainsi, la recherche d’optimisation s’est orientée vers la réduction d’énergie des liens étant donné leur importante contribution énergétique dans la consommation d’énergie dynamique du réseau. De plus, la part de l’énergie dynamique tend à augmenter avec l’évolution de la technologie. Nous avons proposé à l’issue de cette étude deux techniques d’optimisation pour les interconnexions du NoC. Ces deux optimisations proposent des compromis énergie / latence différents et une extension possible de ces travaux pourrait être la mise en oeuvre de la sélection de l’optimisation selon les besoins de l’application en cours. / Thanks to the technology’s shrinking, a considerable amount of memory and computing capacity can be embedded into a single chip. This improvement leads to an important increase of the bandwidth requirements, that becomes the bottleneck of chip performances in terms of computational power. Thus, designers proposed the Network-on-Chip (NoC) as an answer to this bandwidth challenge. However, the on-chip traffic growth allowed by the NoC causes a significant rise of the chip energy consumption, which leads to a temperature increase and a reliability reduction of the chip. The development of energy optimization techniques for NoC becomes necessary.The first part of this thesis is devoted to the study of NoCs power models in order to estimate accurately the consumption of each component. Then, we can identify which ones are the most power consuming. Hence, the first contribution of this thesis has been to improve the NoC power model by replacing the lilnk power model in a NoC simulator (Noxim) by a bit-accurate one (Noxim-XT). In this way, the simulator is able to consider Crosstalk effects, a physical phenomenon that increases links energy consumption. The second part of the thesis deals with NoC energy optimization techniques. Thus, our research of optimization techniques is focused on inter-router links since their energy contribution regarding the NoC dynamic energy is significant and the dynamic energy tends to stay prominent with the shrinking technology. We proposed two optimization techniques from the study of NoC links optimizations. These two techniques present different energy / latency compromises and a possible extension of this work could be the development of a transmission strategy in order to select the right technique according to the application requirements.