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Parallel acceleration of deadlock detection and avoidance algorithms on GPUsAbell, Stephen W. 08 1900 (has links)
Indiana University-Purdue University Indianapolis (IUPUI) / Current mainstream computing systems have become increasingly complex. Most of which have Central Processing Units (CPUs) that invoke multiple threads for their computing tasks. The growing issue with these systems is resource contention and with resource contention comes the risk of encountering a deadlock status in the system. Various software and hardware approaches exist that implement deadlock detection/avoidance techniques; however, they lack either the speed or problem size capability needed for real-time systems. The research conducted for this thesis aims to resolve issues present in past approaches by converging the two platforms (software and hardware) by means of the Graphics Processing Unit (GPU). Presented in this thesis are two GPU-based deadlock detection algorithms and one GPU-based deadlock avoidance algorithm. These GPU-based algorithms are: (i) GPU-OSDDA: A GPU-based Single Unit Resource Deadlock Detection Algorithm, (ii) GPU-LMDDA: A GPU-based Multi-Unit Resource Deadlock Detection Algorithm, and (iii) GPU-PBA: A GPU-based Deadlock Avoidance Algorithm. Both GPU-OSDDA and GPU-LMDDA utilize the Resource Allocation Graph (RAG) to represent resource allocation status in the system. However, the RAG is represented using integer-length bit-vectors. The advantages brought forth by this approach are plenty: (i) less memory required for algorithm matrices, (ii) 32 computations performed per instruction (in most cases), and (iii) allows our algorithms to handle large numbers of processes and resources. The deadlock detection algorithms also require minimal interaction with the CPU by implementing matrix storage and algorithm computations on the GPU, thus providing an interactive service type of behavior. As a result of this approach, both algorithms were able to achieve speedups over two orders of magnitude higher than their serial CPU implementations (3.17-317.42x for GPU-OSDDA and 37.17-812.50x for GPU-LMDDA). Lastly, GPU-PBA is the first parallel deadlock avoidance algorithm implemented on the GPU. While it does not achieve two orders of magnitude speedup over its CPU implementation, it does provide a platform for future deadlock avoidance research for the GPU.
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Design, development and experimentation of a discovery service with multi-level matchingPileththuwasan Gallege, Lahiru Sandakith 20 November 2013 (has links)
Indiana University-Purdue University Indianapolis (IUPUI) / The contribution of this thesis focuses on addressing the challenges of improving and integrating the UniFrame Discovery Service (URDS) and Multi-level Matching (MLM) concepts. The objective was to find enhancements for both URDS and MLM and address the need of a comprehensive discovery service which goes beyond simple attribute based matching. It presents a detailed discussion on developing an enhanced version of URDS with MLM (proURDS). After implementing proURDS, the thesis includes details of experiments with different deployments of URDS components and different configurations of MLM. The experiments and analysis were carried out using proURDS produced MLM contracts. The proURDS referred to a public dataset called QWS dataset. This dataset includes actual information of software components (i.e., web services), which were harvested from the Internet. The proURDS implements the different matching operations as independent operators at each level of matching (i.e., General, Syntactic, Semantic, Synchronization, and QoS). Finally, a case study was carried out with the deployed proURDS. The case study addresses real world component discovery requirements from the earth science domain. It uses the contracts collected from public portals which provide geographical and weather related data.
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Modeling, Analysis, and Simulation of Two Connected Intersections Using Discrete and Hybrid Petri NetsYaqub, Omar Seddeq Omar 29 January 2014 (has links)
Indiana University-Purdue University Indianapolis (IUPUI) / In recent decades, Petri nets (PNs) have been used to model traffic networks for different purposes, such as signal phase control, routing, and traffic flow estimation, etc. Because of the complex nature of traffic networks where both discrete and continuous dynamics come into play, the Hybrid Petri net (HPN) model becomes an important tool for the modeling and analysis of traffic networks. In Chapter 1 a brief historical summery about traffic systems control and then related work is mentioned followed by the major contributions in this research. Chapter 2 provides a theoretical background on Petri nets. In Chapter 3, we develop a HPN model for a single signalized intersection first, then we extend this model to study a simple traffic network that consists of two successive intersections. Time delays between different points of network are also considered in order to make the model suitable for analysis and simulation. In addition to HPN models, we also consider discrete Petri nets where their modeling simplicity enables the characterization of the occurrences of all events in the system. This discrete PN is particularly useful to give a higher-level representation of the traffic network and study its event occurrences and correlations. In Chapter 4, we build a discrete PN model to represent a traffic network with two successive intersections. However, we find that the model leads to unbounded places which cannot accurately reflect the dynamics of the traffic in terms of event occurrences. Hence, we introduce the Modified Binary Petri nets (MBPN) to overcome the limitation and resolve the confliction problem when we design our controllers. This MBPN model is a powerful tool and can be useful for the modeling and analysis of many other applications in traffic networks. Chapter 5 gives a summary for each chapter, provides conclusion and discusses future work for both discrete and hybrid Petri nets.
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