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Matrix and tensor accelerators play indispensable roles in the field of artificial intelligence (AI). Although most of the matrix accelerators, such as graphic processing units (GPUs) and tensor processing units (TPUs), are still electronics based, the energy efficiency and scalability limits of electronic accelerators have presented an opportunity for photonics to perform matrix and tensor acceleration. This dissertation explores silicon photonics as an enabling and cost-effective platform for developing photonic systems, in particular, photonic tensor accelerators. The thesis presents a detailed design procedure for active and passive components, forming a comprehensive Process Design Kit (PDK) in a foundry-compatible silicon photonic platform. The PDK library includes passive waveguide building blocks as well as active components such as micro ring modulators with an EO bandwidth of more than 20GHz and Ge-on-Si photodetectors with >25GHz bandwidth. Having our own PDK ensures consistency in the layout and fabrication of silicon photonic integrated circuits (PIC) across different foundries. We designed and fabricated multidimensional photonic tensor accelerators, each of which consists of many waveguides, splitters/couplers, coherent modulators, and balanced detectors, and successfully demonstrated PIC-based matrix-vector multiplications.

In this thesis, we demonstrate a new type of resonant, nonlinear, light-matter interaction facilitated by the unique electromagnetic vacuum density-of-state (DOS) structure of Photonic Band Gap (PBG) materials. Strong light localization inside PBG waveguides allows extremely strong coupling between laser fields and embedded two-level quantum dots (QD). The resulting Mollow splitting is large enough to traverse the precipitous DOS jump created by a waveguide mode cutoff. This allows the QD Bloch vector to sense the non-smoothness of the vacuum structure and evolve in novel ways that are forbidden in free space. These unusual strong-coupling effects are described using a "vacuum structure term" of the Bloch equation, combined with field-dependent relaxation rates experienced by the QD Bloch vector. This leads to alternation between coherent evolution and enhanced relaxation. As a result, dynamic high-contrast switching of QD populations can be realized with a single beam of picosecond pulses. During enhanced relaxation to a slightly inverted steady state at the pulse peak, the Bloch vector rapidly switches from anti-parallel to parallel alignment with the pulse torque vector. This then leads to a highly inverted state through subsequent coherent "adiabatic following" near the pulse tail, providing a robust mechanism for picosecond, femto-Joule all-optical switching. The simultaneous input of a second, weaker (signal) driving beam at a different frequency on top of the stronger (holding) beam enables rich modulation effects and unprecedented coherent control over the QD population. This occurs through resonant coupling of the signal pulse with the Mollow sideband transitions created by the holding pulse, leading to either augmentation or negation of the final QD population achieved by the holding pulse alone. This effect is applied to ultrafast all-optical logic AND, OR and NOT gates in the presence of significant (0.1 THz) nonradiative dephasing and (about 1%) inhomogeneous broadening. Further numerical studies of pulse evolutions inside the proposed devices demonstrate satisfactory population contrast within a PBG waveguide length of about 10 micro meter. These results provide the building blocks for low-power, ultrafast, multi-wavelength channel, on-chip, all-optical computing.

In this thesis, we demonstrate a new type of resonant, nonlinear, light-matter interaction facilitated by the unique electromagnetic vacuum density-of-state (DOS) structure of Photonic Band Gap (PBG) materials. Strong light localization inside PBG waveguides allows extremely strong coupling between laser fields and embedded two-level quantum dots (QD). The resulting Mollow splitting is large enough to traverse the precipitous DOS jump created by a waveguide mode cutoff. This allows the QD Bloch vector to sense the non-smoothness of the vacuum structure and evolve in novel ways that are forbidden in free space. These unusual strong-coupling effects are described using a "vacuum structure term" of the Bloch equation, combined with field-dependent relaxation rates experienced by the QD Bloch vector. This leads to alternation between coherent evolution and enhanced relaxation. As a result, dynamic high-contrast switching of QD populations can be realized with a single beam of picosecond pulses. During enhanced relaxation to a slightly inverted steady state at the pulse peak, the Bloch vector rapidly switches from anti-parallel to parallel alignment with the pulse torque vector. This then leads to a highly inverted state through subsequent coherent "adiabatic following" near the pulse tail, providing a robust mechanism for picosecond, femto-Joule all-optical switching. The simultaneous input of a second, weaker (signal) driving beam at a different frequency on top of the stronger (holding) beam enables rich modulation effects and unprecedented coherent control over the QD population. This occurs through resonant coupling of the signal pulse with the Mollow sideband transitions created by the holding pulse, leading to either augmentation or negation of the final QD population achieved by the holding pulse alone. This effect is applied to ultrafast all-optical logic AND, OR and NOT gates in the presence of significant (0.1 THz) nonradiative dephasing and (about 1%) inhomogeneous broadening. Further numerical studies of pulse evolutions inside the proposed devices demonstrate satisfactory population contrast within a PBG waveguide length of about 10 micro meter. These results provide the building blocks for low-power, ultrafast, multi-wavelength channel, on-chip, all-optical computing.

The reversible logic has promising applications in emerging computing paradigms, such as quantum computing, quantum dot cellular automata, optical computing, etc. In reversible logic gates, there is a unique one-to-one mapping between the inputs and outputs. To generate a useful gate function, the reversible gates require some constant ancillary inputs called ancilla inputs. Also to maintain the reversibility of the circuits some additional unused outputs are required that are referred to as the garbage outputs. The number of ancilla inputs, the number of garbage outputs and quantum cost plays an important role in the evaluation of reversible circuits. Thus minimizing these parameters are important for designing an efficient reversible circuit. Reversible circuits are of highest interest in optical computing, quantum dot cellular automata and quantum computing. The quantum gates perform an elementary unitary operation on one, two or more two-state quantum systems called qubits. Any unitary operation is reversible in nature, and hence, quantum networks are also reversible, to conclude the quantum computers must be built from reversible logic components. The main contribution of this dissertation is the design exploration and application of reversible circuits in emerging nanotechnologies. The emerging technologies explored in this work are 1) Optical quantum computing 2) Quantum computing. The first contribution of this dissertation is Mach-Zehnder interferometer based design of all optical reversible binary adder. The all optical reversible adder design is based on two new optical reversible gates referred as optical reversible gate I (ORG-I) and optical reversible gate II (ORG-II) and the existing all optical Feynman gate. The two new reversible gates ORG-I and ORGI-II have been proposed and can implement a reversible adder with a reduced optical cost which is equal to the number of MZI switches required, less propagation delay, and with zero overhead in terms of number of ancilla inputs and the garbage outputs. The proposed all optical reversible adder design based on the ORG-I and ORG-II reversible gates are compared and shown to be better than the other existing designs of reversible adder proposed in the non-optical domain in terms of number of MZI switches, delay, the number of ancilla inputs and the garbage outputs. The proposed all optical reversible adder will be a key component of an all optical reversible arithmetic logical unit (ALU), that is a quite essential component in a wide variety of optical signal processing applications. In the existing literature, the NAND logic based implementation is the only known implementation available for reversible gates and its functions. There is a lack of research in the direction of NOR logic based implementation of reversible gates and functions. The second contribution of this dissertation is the design of NOR logic based n-input and n-output reversible gates, one of which can be efficiently mapped into optical computing using the Mach-Zehnder interferometer (MZI), while the other can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with less number of linear optical quantum logic gates with reduced optical cost and propagation delay compared to the implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach-Zehnder interferometer. The third contribution of this dissertation is a binary tree-based design methodology for a NxN reversible multiplier. The proposed binary tree-based design methodology for a NxN reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit; thereby, minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows improvements in terms of number of ancilla inputs and garbage outputs compared to all the existing reversible multiplier designs. The methodology is also extended to the design of NxN reversible signed multiplier based on modified Baugh-Wooley multiplication methodology.

<p>FRET-enabled optical computing is a new computing paradigm that uses the energy of incident photons to perform computation in molecular-scale circuits composed of inter-communicating photoactive molecules. Unlike conventional computing approaches, computation in these circuits does not require any electric current; instead, it relies on the controlled-migration of energy in the circuit through a phenomenon called Förster Resonance Energy Transfer (FRET). This, coupled with other unique features of FRET circuits can enable computing in new domains that are unachievable by the conventional semiconductor-based computing, such as in-cell computing or targeted drug delivery. In this thesis, we explore novel FRET-based multiplexing techniques to significantly increase the storage density of optical storage media. Further, we develop analysis algorithms, and computer-aided design tools for FRET circuits.</p><p>Existing computer-aided design tools for FRET circuits are predominantly ad hoc and specific to particular functionalities. We develop a generic design-automation framework for FRET-circuit optimization that is not limited to any particular functionality. We also show that within a fixed time-budget, the low-speed of Monte-Carlo-based FRET-simulation (MCS) algorithms can have a potentially-significant negative impact on the quality of the design process, and to address this issue, we design and implement a fast FRET-simulation algorithm which is up to several million times faster than existing MCS algorithms. We finally exploit the unique features of FRET-enabled optical computing to develop novel multiplexing techniques that enable orders of magnitude higher storage density compared to conventional optical storage media, such as DVD or Blu-Ray.</p> / Dissertation

A complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor could be implemented, was proposed. Following the new polarization-based representation, a new Orthoparallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output once in a truth table, was developed. This representation allows for the implementation of all basic 16 logic gates, including the NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented, which opens the door for reconfigurable optical processors and programmable optical logic gates. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. The Rail Road (RR) architecture for polarization optical processors (POP) is presented. All the control inputs are applied simultaneously, leading to a single time lag, which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step design algorithm is provided for the POP, and design reduction methodologies are discussed. The algorithm lends itself systematically to software programming and computer-assisted design. A completely passive optical switch was also proposed. The switch is used to design completely passive optical gates, including the NAND gate, with their operational speeds only bound by the input beams prorogation delay. The design is used to demonstrate various circuits including the RS latch. Experimental data is reported for the NAND and the Universal gate operating with different functionality. A minute error is recorded in different cases, which can be easily eliminated by a more dedicated manufacturing process. Finally, some field applications are discussed and a comparison between all proposed systems and the current semiconductor devices is conducted based on multiple factors, including, speed, lag, and heat generation.