Stuttgart, Univ., Fakultät Informatik, Diplomarb., 1997.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In order to reduce the ground segment equipment cost for small space missions, the French national space center (CNES) had the need to develop a CCSDS down-link interface board for low telemetry rates (< 1.5 Mb/s). This board performs frame synchronization and Reed-Solomon decoding. An important part of this design was the Reed-Solomon decoder development. In order to maintain low recurrent cost for this board, this decoder was realized in FPGA technology. Reed-Solomon decoding function, interleaving function (from 1 to 5) and virtual fill management are included in the same component. All set-up parameters are software programmable via the PCI bus, data and status are also available via the PCI bus under windows NT operating system. This paper presents the main features of this board and an overview of the Reed-Solomon decoder development.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / The Space Sensing & Vehicle Control Branch of the Air Force Research Laboratory and Voss Scientific, Albuquerque, NM, are developing an advanced PC and COTS-based satellite telemetry processing, analysis and display system known as the PC-Satellite Telemetry Server (PC-STS). This program grew out of a need to develop less expensive, more capable, more flexible, and expandable solutions to the satellite telemetry analysis requirements of the Air Force. Any new system must employ industry standard, open architecture, network and database protocols allowing for easy growth and migration to new technologies, as they become available. Thus, the PC-STS will run on standard personal computers and the Windows NT operating system. The focus of this work and this paper is the Telemetry Server component, and in particular, the custom-built decommutation board. The decommution board will be capable of processing frame formatted and CCSDS packet telemetry. It will be capable of fully decommutating telemetry data, converting raw data to engineering units, and providing this data to the Telemetry Server host. Time tagged engineering units or minor frames of telemetry will be transmitted to the Telemetry Server processor via on-board memory buffers. The decom board uses the PCI bus, programmable DSPs, considerable on-board memory, and a SCSI bus for local archiving. This paper presents the general architecture of the PC-STS, and discusses specific design considerations. These include trade-offs made during the design of the board’s hardware and software, operational specifications, and graphical user interfaces to program, monitor, and control the board.

Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2004. / Includes bibliographical references (leaf 89). / This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. / This thesis project involves the architecture, implementation, and verification of a high bandwidth, low cost ASIC digital logic core that is compliant with the PCI Express to PCIX Bridge Specification. The core supports PCI Express and PCIX transactions, x16 PCI Express link widths, 32 and 64-bit PCIX link widths, all PCI Express and PCIX packet sizes, transaction ordering and queuing, relaxed ordering, flow control, and buffer management. Performance and area are optimized at the architectural and logic levels. The core is approximately 27K gate count, runs at a maximum of 250 MHz, and is synthesized to a current standard technology. This thesis explores PCI Express, PCIX, and PCI technologies, architectural design, development of Verilog and Vera models, thorough module-level verification, the development of a PCI Express/PCIX system verification environment, synthesis, static timing analysis, and performance and area evaluations. The work has been completed in IBM Microelectronics in Burlington, Vermont as part of the MIT VI-A Program. / by Margaret J. Chong. / M.Eng.and S.B.

Mannheim, Univ., Diss., 2004.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The trend of current data acquisition and recording systems is to capture multiple streams of Pulse Code Modulation (PCM) data on a single media. The MARS II data recording system manufactured by Datatape, the Asynchronous Realtime Multiplexer and Output Reconstructor (ARMOR) systems manufactured by Calculex, Inc., and other systems on the market today are examples of this technology. The quantity of data recorded by these systems can be impressive, and can cause difficulties in post-test data processing in terms of data storage and turn around time to the analyst. This paper describes the system currently in use at the Strategic Systems Combined Test Force B-1B division to simultaneously post-flight process up to twelve independent PCM streams at twice real-time speeds. This system is entirely personal computer (PC) based running the Window NT 4.0 operating system with an internal ISA bus PCM decommutation card. Each PC is capable of receiving and processing one stream at a time. Therefore, the core of the system is twelve PCs each with decommutation capability. All PCs are connected via a fast ethernet network hub. The data processed by this system is IRIG 106 Chapter 8 converted MIL-STD-1553B bus data and Chapter 4 Class I and II PCM data. All system operator inputs are via Distributed Component Object Modeling (DCOM) provided by Microsoft Developers Studio, Versions 5.0 and 6.0, which allows control and status of multiple data processing PCs from one workstation. All data processing software is written in-house using Visual C++ and Visual Basic.

Thesis--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 67-68).

University, Diss., 2005--Mannheim. / Erscheinungsjahr an der Haupttitelstelle: 2004.

This thesis deals with the communication on the PCI bus and the design of controllers for the PCI card with FPGA circuit. The introduction shows the functionality and structure of FPGA circuits, followed by description of the principle of communication through the PCI bus. After an analysis of the PCI the thesis describes a design of controllers for a target card and lets the reader get acquainted with its different parts. In the process of implementation carefully examines the structure and operation of individual blocks of PCI controller. In the following part the thesis shows the process of implementation and testing of the final solution using the educational card with FPGA circuit.