Master of Science / Department of Electrical and Computer Engineering / Don M. Gruenbacher / This thesis presents a novel device for delaying Ethernet traffic in a lab setting. Ethernet is the leading standard for communications between computing devices. With the advent of streaming media such as voice over IP phone service and real-time control systems over Ethernet, applications are being rapidly developed that must meet strict communication reliability and timing constraints. Increasingly, these systems must be examined in real world scenarios before actual hardware deployment or protocol release. This increases the demand for both testing equipment and well trained network engineers. Commercial Ethernet delay testing devices are expensive, hardware specific, and not flexible enough for educational purposes. These short-comings make it necessary to design a robust Field Programmable Gate Array (FPGA) based Ethernet delay device that is up to the rigor of educational and research settings. Our approach is based on the inexpensive, high performance Altera Stratix II GX PCI Express development board which can easily be adapted for different delay scenarios. The system's FPGA hardware was developed in Verilog, an industry standard hardware description language, so users will be able to quickly learn, adapt and operate the system. Software for the system's soft processor was developed in C. The device provides a wide range of packet delay from nearly zero up to over fifty milliseconds, as well as providing an easy to use interface with on-the-fly variable delay adjustment. Theoretical throughput was up to 1Gb/s; skew and jitter measurements were comparable with common network switches. These properties allow the device to provide an easy-to-use, inexpensive method to delay Ethernet traffic in lab settings and the device also creates a starting point for future students and researchers to develop high speed traffic delay testbeds. Future work will include 10Gb/s throughput, additional memory capacity and additional software implemented delay profiles.

Tactical radio communications used in military applications hasstrict requirements regarding security and has to be operable inrough environments in which there may be disturbances and disruptionson a radio link. The performance of the Secure CommunicationInteroperability Protocol (SCIP) operating in an asynchronouscommunication network with various levels of packet loss isinvestigated and found inadequate mainly due to problems withcryptographic synchronization between the transmitting and receivingunits. The introduction of additional counter data to each datapacket remedies this problem and allows the receiving units to fillthe holes left by packet losses with filler packets, maintainingsynchronization. The audio quality can then be measured using thePerceptual Evaluation of Speech Quality (PESQ) algorithm.Measurements are performed in an emulated radio link with aconfigurable packet loss ratio developed by Saab. The results showthat parts of SCIP can be used alongside the counter solution withoutimpacting the audio quality. The insertion of filler packets is shownto have a positive effect on the audio quality, while aggregation ofpackets to conserve transmission data rate is shown to have anegative effect.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

在如同全IP網路(ALL-IP Network)這類的分封交換網路(packet-switching network)中提供具時效性的服務(time-sensitive services)必須嚴格的控制時間。路由規劃是網路管理中重要的一環，所以這類網路的路由規劃必須考慮網路延遲。然而就我們目前所知，多數的傳統路由演算法並不以傳輸延遲(path delay)為主要考量因素；例外少數有考量延遲時間的演算法也僅限於鍊結延遲(link delay)，而未考慮節點延遲(node delay)。此乃肇因於以往頻寬的成本極為昂貴，因而造成演算法設計者在設計時會儘可能有效利用頻寬，如此免不了會犧牲傳遞速度。在過去幾年間，由於光通訊技術的提升，網路頻寬的成長速度遠遠已超過路由器(router)處理能力的成長。在這樣不對等的成長比例驅使下，節點延遲，亦即路由器處理封包時所耗時間，在傳輸延遲中所佔的比例亦隨之快速增長。也因此我們認為，在為高速封包交換網路設計路由演算法時，必須同時考量鍊結延遲和節點延遲。在本論文中，我們設計了一個訊務流為基礎的路由演算法(flow-based routing algorithm)，KLONE，來驗證我們的論點。在規劃路由時，KLONE會把發生在鍊結和節點上的延遲時間一併列入計算，並以全體延遲時間為主要考量。透過我們反覆的測試實驗，我們發現其較之於常用的OSPF演算法，可以在效能上有30%的勝出。藉此，我們的論點得到初步的證實。 / Providing time sensitive services becomes an essential task for some packet-switching networks such as All-IP networks, which will carry all the traffics supported by both circuit-switching and packet-switching networks. To fulfill this demand, such networks require a delay sensitive routing mechanism to provide time-related QoS for delay sensitive services. However, most of traditional routing algorithms do not take delay time as a major concern. Only a few are designed for time sensitive services. These time sensitive routing algorithms are designed at the time when the link bandwidth is the only scarce resource. As the bandwidth of communication links grows rapidly in recent years due to the advance of optical communication technologies, link bandwidth is no longer the only scarce resource. The processing speed of nodes, for example, routers, becomes another critical source of delay time. In this thesis, we designed a new flow-based routing algorithm, the KLONE algorithm, which takes average delay time as its minimization objective and takes both nodes and links as delay components. Through an intensive evaluation using simulation method, we demonstrate that a routing algorithm that considers both link and node delay might outperform the traditional OSPF algorithm.

No description available.

The object of interest in this research is the evaluation of the combined routing and flow control scheme proposed by Muralidhar and Sundareshan. A slightly modified design using results from positive system theory is proposed as an attempt to improve the performance. Then a detailed performance evaluation of Muralidhar and Sundareshan's scheme and its modified version proposed here is conducted using discrete-event simulation. The application of positive system theory to the combined routing and flow control algorithm proposed by Muralidhar and Sundareshan proved to be quite effective in improving the overall performance only in the initial transient period. The fact that the improvement is restricted to a particular time period appears to be attributable to poor buffer management and certain other fundamental problems with Muralidhar and Sundareshan's scheme. These problems are identified and are described in detail.

No description available.

No description available.

by Ngai Tin Yee. / Bibliography: leaves [28]-[29] / Thesis (M.Ph.)--Chinese University of Hong Kong, 1984

Yuen Ching Wan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 77-83). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Nature of Real-Time Traffic --- p.1 / Chapter 1.2 --- Delay Variability in Wireless Networks --- p.2 / Chapter 1.2.1 --- Propagation Medium --- p.3 / Chapter 1.2.2 --- Impacts of Network Designs --- p.5 / Chapter 1.3 --- The Keys - Packet Lifetime & Channel State --- p.8 / Chapter 1.4 --- Contributions of the Thesis --- p.8 / Chapter 1.5 --- Organization of the Thesis --- p.9 / Chapter 2 --- Background Study --- p.11 / Chapter 2.1 --- Packet Scheduling --- p.12 / Chapter 2.2 --- Call Admission Control (CAC) --- p.12 / Chapter 2.3 --- Active Queue Management (AQM) --- p.13 / Chapter 2.3.1 --- AQM for Wired Network --- p.14 / Chapter 2.3.2 --- AQM for Wireless Network --- p.17 / Chapter 3 --- Intelligent Packet Discarding Policies --- p.21 / Chapter 3.1 --- Random Packet Discard --- p.22 / Chapter 3.1.1 --- Variable Buffer Limit (VABL) --- p.22 / Chapter 3.2 --- Packet Discard on Expiration Likelihood (PEL) --- p.23 / Chapter 3.2.1 --- Working Principle --- p.24 / Chapter 3.2.2 --- Channel State Aware Packet Discard on Expiration Likelihood (CAPEL) --- p.26 / Chapter 3.3 --- System Modeling --- p.29 / Chapter 3.3.1 --- Wireless Channel as an Markov-Modulated Poisson Process (MMPP) --- p.30 / Chapter 3.3.2 --- System Analysis --- p.30 / Chapter 3.3.3 --- System Time Distribution --- p.33 / Chapter 3.3.4 --- Approximation of System Time Distribution by Gamma Distribution --- p.36 / Chapter 3.4 --- Goodput Analysis of Intelligent Packet Discarding Policies --- p.38 / Chapter 3.4.1 --- Variable Buffer Limit (VABL) --- p.38 / Chapter 3.4.2 --- CAPEL at the End-of-Line --- p.39 / Chapter 3.4.3 --- CAPEL at the Head-of-Line --- p.43 / Chapter 4 --- Performance Evaluation --- p.44 / Chapter 4.1 --- Simulation --- p.44 / Chapter 4.1.1 --- General Settings --- p.45 / Chapter 4.1.2 --- Choices of Parameters --- p.46 / Chapter 4.1.3 --- Variable Buffer Limit (VABL) --- p.49 / Chapter 4.1.4 --- CAPEL at the End-of-Line --- p.53 / Chapter 4.1.5 --- CAPEL at the Head-of-Line --- p.60 / Chapter 4.2 --- General Discussion --- p.64 / Chapter 4.2.1 --- CAPEL vs RED --- p.64 / Chapter 4.2.2 --- Gamma Approximation for System Time Distribution . --- p.69 / Chapter 5 --- Conclusion --- p.70 / Chapter A --- Equation Derivation --- p.73 / Chapter A.l --- Steady State Probabilities --- p.73 / Bibliography --- p.77