by Lau Chu Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 76-83). / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Basic Notions --- p.13 / Chapter 3 --- Fast Knockout --- p.19 / Chapter 3.1 --- The Algorithm of Fast Knockout --- p.20 / Chapter 3.2 --- Complexity of the Fast Knockout Algorithm --- p.29 / Chapter 3.3 --- Summary --- p.35 / Chapter 4 --- k-Sortout --- p.36 / Chapter 4.1 --- A Brief Review of k-Sorting --- p.37 / Chapter 4.2 --- The Algorithm of k-Sortout --- p.47 / Chapter 4.3 --- Complexity of the k- Sortout Algorithm --- p.53 / Chapter 4.4 --- Summary --- p.58 / Chapter 5 --- General Sortout --- p.59 / Chapter 5.1 --- The General Algorithm of Sortout --- p.59 / Chapter 5.2 --- Complexity of Concentrators by the General Algorithm --- p.64 / Chapter 5.3 --- Summary --- p.69 / Chapter 6 --- Concluding Remarks --- p.70 / Chapter 6.1 --- Summary of Results --- p.70 / Chapter 6.2 --- Directions for Further Research --- p.73 / Bibliography --- p.76

by Yeung Ming Sang. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 191-[201]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.1.1 --- Broadband Integrated Services Network --- p.1 / Chapter 1.1.2 --- ATM Switching Technology --- p.3 / Chapter 1.2 --- Broadband ATM Switching ´ؤ A Review --- p.4 / Chapter 1.2.1 --- Shared Memory Switches --- p.5 / Chapter 1.2.2 --- Shared Medium Switches --- p.5 / Chapter 1.2.3 --- Space-division Type Switches --- p.6 / Chapter 1.3 --- Motivation and Contributions --- p.13 / Chapter 1.4 --- Overview of the Thesis --- p.13 / Chapter 2 --- Pipeline Banyan Switch Architecture --- p.15 / Chapter 2.1 --- Switch Architecture --- p.15 / Chapter 2.2 --- Switch Operation --- p.17 / Chapter 2.3 --- Switch Design --- p.19 / Chapter 2.4 --- "Priority, Broadcasting and Multicasting Mechanisms" --- p.21 / Chapter 2.5 --- Switch Speed Reduction at the Control Plane --- p.23 / Chapter 3 --- Performance Evaluation of Pipeline Banyan --- p.27 / Chapter 3.1 --- Performance under Uniform and Independent Traffic Pattern --- p.27 / Chapter 3.1.1 --- Analysis of Packet Loss Performance --- p.27 / Chapter 3.1.2 --- Throughput Performance --- p.32 / Chapter 3.1.3 --- Delay Performance --- p.36 / Chapter 3.1.4 --- Comparison of Loss Performance of Banyan-type Networks --- p.37 / Chapter 3.1.5 --- Output Queueing Capability --- p.41 / Chapter 3.2 --- Performance of the Switch under Special Traffic Pattern --- p.45 / Chapter 3.2.1 --- Performance under Bursty Traffic --- p.45 / Chapter 3.2.2 --- Performance under Hot Spot Traffic --- p.48 / Chapter 3.2.3 --- Performance under Point-to-Point Traffic --- p.51 / Chapter 3.2.4 --- Performance under Permutation Traffic --- p.52 / Chapter 3.3 --- Switch Complexity Discussion --- p.54 / Chapter 4 --- Multi-Channel Pipeline Banyan (MCPB) --- p.57 / Chapter 4.1 --- Background --- p.57 / Chapter 4.2 --- Switch Architecture --- p.59 / Chapter 4.3 --- Performance Evaluation --- p.64 / Chapter 4.3.1 --- Packet loss probability --- p.64 / Chapter 4.3.2 --- Throughput performance --- p.69 / Chapter 4.3.3 --- Delay performance --- p.69 / Chapter 4.4 --- Application of MCPB --- p.71 / Chapter 4.4.1 --- ATM Cross-connect --- p.71 / Chapter 4.4.2 --- Switch Interconnection Fabric --- p.71 / Chapter 5 --- VLSI Implementation --- p.75 / Chapter 5.1 --- Outline of a typical ATM switching system --- p.75 / Chapter 5.1.1 --- Line Interface Module --- p.75 / Chapter 5.1.2 --- System Manager Module --- p.77 / Chapter 5.1.3 --- Switch Module --- p.78 / Chapter 5.2 --- "VLSI Design Technology, Procedures and Tools" --- p.78 / Chapter 5.2.1 --- Design Technology --- p.78 / Chapter 5.2.2 --- Procedures and Tools --- p.79 / Chapter 5.3 --- Logic Design of ATM Switch Module --- p.80 / Chapter 5.3.1 --- Switching Element in Control Plane --- p.80 / Chapter 5.3.2 --- Switching Element in Data Plane --- p.86 / Chapter 5.3.3 --- Clock Generator for Synchronization --- p.93 / Chapter 5.3.4 --- Schematic of Control Plane --- p.98 / Chapter 5.3.5 --- Schematic of Data Plane --- p.98 / Chapter 5.3.6 --- Timing Diagrams --- p.98 / Chapter 5.4 --- Chip Summary --- p.107 / Chapter 5.5 --- Experiences --- p.109 / Chapter 5.5.1 --- Core Size Limitation --- p.109 / Chapter 5.5.2 --- Pin Count Limitation --- p.110 / Chapter 5.5.3 --- Speed Limitation --- p.111 / Chapter 5.5.4 --- Other Design Considerations --- p.111 / Chapter 5.6 --- Discussions --- p.112 / Chapter 6 --- Dynamic Priority Schemes for Fast Packet Switches --- p.114 / Chapter 6.1 --- Motivation --- p.114 / Chapter 6.2 --- Switch Architecture --- p.118 / Chapter 6.3 --- QCPD: Queueing Controlled Priority Discipline --- p.121 / Chapter 6.3.1 --- Algorithm QCPD --- p.121 / Chapter 6.4 --- BCPD: Blocking Controlled Priority Discipline --- p.122 / Chapter 6.4.1 --- Algorithm BCPD_FT --- p.122 / Chapter 6.4.2 --- Delay Guarantee by Algorithm BCPD_FT --- p.123 / Chapter 6.4.3 --- Algorithm BCPD_DT --- p.126 / Chapter 6.4.4 --- Delay Guarantee by Algorithm BCPD_DT --- p.128 / Chapter 6.5 --- HCPD: Hybrid Controlled Priority Discipline --- p.134 / Chapter 6.5.1 --- Algorithms HCPD_FT and HCPD_DT --- p.135 / Chapter 6.6 --- Performance Studies --- p.136 / Chapter 6.6.1 --- Performance Comparison of the Priority Schemes --- p.136 / Chapter 6.6.2 --- Cell Loss Performance of HCPD_DT --- p.140 / Chapter 6.6.3 --- Input Queue Distribution of HCPD_DT --- p.142 / Chapter 6.6.4 --- Delay Bound of HCPD_DT --- p.144 / Chapter 6.6.5 --- Performance of HCPD_DT under Priority Traffic --- p.148 / Chapter 6.7 --- The use of HCPD_DT in Pipeline Banyan --- p.152 / Chapter 6.8 --- Conclusion --- p.153 / Chapter 7 --- Summary and Future Work --- p.155 / Chapter 7.1 --- Summary --- p.155 / Chapter 7.2 --- Future Work --- p.156 / Chapter A --- Verilog HDL descriptions of 16x16 Pipeline Banyan --- p.158 / Chapter B --- User's Guide of 16x16 Pipeline Banyan Chip Set --- p.182 / Chapter B.l --- Specification --- p.182 / Chapter B.2 --- Control Plane Chip and Data Plane Chip Pinout --- p.183 / Chapter B.2.1 --- Control Plane Chip Pinout --- p.183 / Chapter B.2.2 --- Data Plane Chip Pinout --- p.183 / Chapter B.3 --- Signal Descriptions --- p.186 / Chapter B.3.1 --- Signal Descriptions of Control Plane Chip --- p.186 / Chapter B.3.2 --- Signal Descriptions of Data Plane Chip --- p.187 / Chapter B.4 --- Connection Examples --- p.188 / Bibliography --- p.191

by Su Chao. / Publication date on spine: 1996. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 164-[165]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Objective of Study --- p.3 / Chapter 1.3 --- The Applications of Burst-Mode Receivers in Optical Networks --- p.6 / Chapter 1.4 --- Preview of Chapters --- p.9 / Chapter 2 --- Theory of Optical Burst-Mode Receivers --- p.14 / Chapter 2.1 --- Introduction --- p.14 / Chapter 2.2 --- Comparison of Continuous and Burst-Mode Data --- p.17 / Chapter 2.3 --- Models for Conventional and Burst-Mode Receiver --- p.20 / Chapter 2.3.1 --- A Conventional Receiver Model --- p.20 / Chapter 2.3.2 --- A Burst-Mode Receiver Model --- p.22 / Chapter 2.4 --- Threshold Variations in Burst-Mode Receivers --- p.24 / Chapter 2.4.1 --- Threshold Setting for a Burst-Mode Receiver --- p.24 / Chapter 2.4.2 --- Degradations of Burst-Mode Receivers Due to the Adap- tive Threshold Setting --- p.26 / Chapter 2.5 --- Theory of BER Performance for Burst-Mode Receivers --- p.31 / Chapter 2.5.1 --- BER Performances for Uncoded and Encoded Input Signals --- p.31 / Chapter 2.5.2 --- Simulation of Error Performance for Burst-Mode Receivers --- p.33 / Chapter 2.6 --- Extinction Ratio Consideration for Burst-Mode Receiver --- p.35 / Chapter 2.7 --- Consideration of Network Capacity Penalty --- p.36 / Chapter 2.8 --- Experimental Results for Burst-Mode Receivers --- p.39 / Chapter 2.8.1 --- BER Measurement Consideration --- p.39 / Chapter 2.8.2 --- Threshold Offset Consideration for Burst-Mode Receivers --- p.41 / Chapter 2.9 --- Chapter Summary --- p.43 / Chapter 3 --- Fast Clock Recovery for Burst-Mode Receivers --- p.55 / Chapter 3.1 --- Introduction --- p.55 / Chapter 3.2 --- Techniques Overview for Fast Clock Recovery --- p.57 / Chapter 3.3 --- Fast Phase Recovery Using Global Clock With Correlator --- p.60 / Chapter 3.4 --- Rapid Clock Recovery Using Narrow-Band Quenched Filter --- p.65 / Chapter 3.5 --- Instantaneous Phase Synchronization Using Gated-Oscillators With PLL --- p.70 / Chapter 3.6 --- Chapter Summary --- p.73 / Chapter 4 --- Multi-Level Signaling and Multi-Level Burst-Mode Receiver --- p.84 / Chapter 4.1 --- Introduction --- p.84 / Chapter 4.2 --- Baseband M-ary Signaling and Its Transmission in Band-Limited Channels --- p.87 / Chapter 4.3 --- Power Spectrum of Digital Multi-Level Baseband Signal --- p.90 / Chapter 4.3.1 --- Power Spectrum of Transmission Line Code --- p.90 / Chapter 4.3.2 --- Power Spectrum of Multi-Level Line Code --- p.91 / Chapter 4.3.3 --- Power Spectra for NRZI and MLT3 Line Codes --- p.93 / Chapter 4.3.4 --- Reduction of DC Component --- p.96 / Chapter 4.4 --- Error Probability of MLT-N Code Using Maximum-Likelihood Sequence Detector --- p.98 / Chapter 4.4.1 --- Overview Maximum-Likelihood Sequence Detector --- p.98 / Chapter 4.4.2 --- Error Probabilities of NRZI and MLT3 --- p.100 / Chapter 4.5 --- Multi-level Burst-Mode Receiver for Multiaccess LANs --- p.103 / Chapter 4.5.1 --- A Survey of Conventional MLT3 Receiver --- p.103 / Chapter 4.5.2 --- Multi-level Burst-Mode Receiver for Metallic Cable --- p.105 / Chapter 4.5.3 --- Multi-Level Burst-Mode Receiver for Optical Fiber Cable --- p.109 / Chapter 4.6 --- Chapter Summary --- p.111 / Chapter 5 --- Conclusion and Future Work --- p.123 / Chapter 5.1 --- Conclusion --- p.123 / Chapter 5.2 --- Future Work --- p.125 / Bibliography --- p.127 / Chapter A --- p.137 / Chapter A.1 --- Supervisory System for Long-Hauled Transmission Systems Using EDFAs --- p.137 / Chapter A.1.1 --- An Overview of System Reliability in Undersea Telecom- munications --- p.138 / Chapter A.1.2 --- Supervisory Signal Transmission in ED FA Systems --- p.139 / Chapter B --- p.146 / Chapter B.1 --- BER Performances for Uncoded and Encoded Data --- p.146 / Chapter B.2 --- mBnB Encoder Table --- p.148 / Chapter B.3 --- Power Penalty Due to Extinction Ratio --- p.150 / Chapter B.4 --- Threshold Offset and Pulse Width Distortion --- p.151 / Chapter B.5 --- Q-function --- p.152 / Chapter C --- p.153 / Chapter C.1 --- BER Performance Using Correlator --- p.153 / Chapter C.2 --- Clock Performance Using Quenched Filter --- p.154 / Chapter C.3 --- BER Performance Using Quenched filter --- p.157 / Chapter D --- p.158 / Chapter D.1 --- """Bit-Stuffing Precoder" --- p.158 / Chapter D.2 --- Threshold Placement of Multilevel Optical Receiver --- p.159 / Chapter E --- List of Publications --- p.164

by Lui Hung Ngai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 56-[59]). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Thesis Overview --- p.3 / Chapter 2 --- Background & Related work --- p.4 / Chapter 2.1 --- Scheduling problem in ATM switch --- p.4 / Chapter 2.2 --- Traffic Scheduling in output-buffered switch --- p.5 / Chapter 2.3 --- Traffic Scheduling in Input buffered Switch --- p.16 / Chapter 3 --- Deadline-ordered Parallel Iterative Matching (DLPIM) --- p.22 / Chapter 3.1 --- Introduction --- p.22 / Chapter 3.2 --- Switch model --- p.23 / Chapter 3.3 --- Deadline-ordered Parallel Iterative Matching (DLPIM) --- p.24 / Chapter 3.3.1 --- Motivation --- p.24 / Chapter 3.3.2 --- Algorithm --- p.26 / Chapter 3.3.3 --- An example of DLPIM --- p.28 / Chapter 3.4 --- Simulation --- p.30 / Chapter 4 --- DLPIM with static scheduling algorithm --- p.41 / Chapter 4.1 --- Introduction --- p.41 / Chapter 4.2 --- Static scheduling algorithm --- p.42 / Chapter 4.3 --- DLPIM with static scheduling algorithm --- p.48 / Chapter 4.4 --- An example of DLPIM with static scheduling algorithm --- p.50 / Chapter 5 --- Conclusion --- p.54 / Bibliography --- p.56

Lau Tsz-ming. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 57-[61]). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Integrated Services Architecture --- p.2 / Chapter 1.2 --- Cross-path Switch --- p.4 / Chapter 1.2.1 --- Path Switching --- p.5 / Chapter 1.3 --- Organization of Thesis --- p.9 / Chapter 2 --- Module Architecture --- p.10 / Chapter 2.1 --- Introduction --- p.10 / Chapter 2.2 --- Notable Features --- p.11 / Chapter 3 --- Connection Admission Control and Resource Allocation --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Connection Admission Control --- p.15 / Chapter 3.2.1 --- Guaranteed Service --- p.15 / Chapter 3.2.2 --- Controlled-Load Service --- p.18 / Chapter 3.3 --- Resource Allocation --- p.27 / Chapter 4 --- Resource Management --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Scheduling Algorithm --- p.32 / Chapter 4.2.1 --- Input and Output Module --- p.32 / Chapter 4.2.2 --- Central Module --- p.34 / Chapter 4.3 --- Buffer Management --- p.39 / Chapter 4.3.1 --- Buffer Partitioning --- p.40 / Chapter 4.3.2 --- Dicard Policy --- p.40 / Chapter 5 --- Design Issue of Cross-path Switch --- p.43 / Chapter 5.1 --- Introduction --- p.43 / Chapter 5.2 --- Stability Condition --- p.44 / Chapter 5.3 --- Supplementary Admission Control Scheme --- p.46 / Chapter 5.4 --- Simulation --- p.50 / Chapter 6 --- Conclusion --- p.55 / Bibliography --- p.57

"Packet loss can be detrimental to real-time interactive video over lossy networks because one lost video packet can propagate errors to many subsequent video frames due to the encoding dependency between frames. Feedback-based error control techniques use feedback information from the decoder to adjust coding parameters at the encoder or retransmit lost packets to reduce the error propagation due to data loss. Feedback-based error control techniques have been shown to be more effective than trying to conceal the error at the encoder or decoder alone since they allow the encoder and decoder to cooperate in the error control process. However, there has been no systematic exploration of the impact of video content and network conditions on the performance of feedback-based error control techniques. In particular, the impact of packet loss, round-trip delay, network capacity constraint, video motion and reference distance on the quality of videos using feedback-based error control techniques have not been systematically studied. This thesis presents analytical models for the major feedback-based error control techniques: Retransmission, Reference Picture Selection (both NACK and ACK modes) and Intra Update. These feedback-based error control techniques have been included in H.263/H.264 and MPEG4, the state of the art video in compression standards. Given a round-trip time, packet loss rate, network capacity constraint, our models can predict the quality for a streaming video with retransmission, Intra Update and RPS over a lossy network. In order to exploit our analytical models, a series of studies has been conducted to explore the effect of reference distance, capacity constraint and Intra coding on video quality. The accuracy of our analytical models in predicting the video quality under different network conditions is validated through simulations. These models are used to examine the behavior of feedback-based error control schemes under a variety of network conditions and video content through a series of analytic experiments. Analysis shows that the performance of feedback-based error control techniques is affected by a variety of factors including round-trip time, loss rate, video content and the Group of Pictures (GOP) length. In particular: 1) RPS NACK achieves the best performance when loss rate is low while RPS ACK outperforms other repair techniques when loss rate is high. However RPS ACK performs the worst when loss rate is low. Retransmission performs the worst when the loss rate is high; 2) for a given round-trip time, the loss rate where RPS NACK performs worse than RPS ACK is higher for low motion videos than it is for high motion videos; 3) Videos with RPS NACK always perform the same or better than videos without repair. However, when small GOP sizes are used, videos without repair perform better than videos with RPS ACK; 4) RPS NACK outperform Intra Update for low-motion videos. However, the performance gap between RPS NACK and Intra Update drops when the round-trip time or the intensity of video motion increases. 5) Although the above trends hold for both VQM and PSNR, when VQM is the video quality metric the performance results are much more sensitive to network loss. 6) Retransmission is effective only when the round-trip time is low. When the round-trip time is high, Partial Retransmission achieves almost the same performance as Full Retransmission. These insights derived from our models can help determine appropriate choices for feedback-based error control techniques under various network conditions and video content. "

Current congestion control approaches that attempt to provide fair bandwidth allocation among competing flows primarily consider only data rate when making decisions on which packets to drop. However, responsive flows with high round trip times (RTTs) can still receive significantly less bandwidth than responsive flows with low round trip times. This paper proposes a congestion control scheme called WHITE that addresses router unfairness in handling flows with significantly different RTTs. Using a best-case estimate of a flow's RTT provided in each packet by the flow source or by an edge router, WHITE computes a stabilized average RTT. The average RTT is then compared with the RTT of each incoming packet, dynamically adjusting the drop probability so as to protect the bandwidth of flows with high RTTs while curtailing the bandwidth of flows with low RTTs. We present simulation results and analysis that demonstrate that WHITE provides better fairness than other rate-based congestion control strategies over a wide-range of traffic conditions. The improved fairness of WHITE comes close to the fairness of Fair Queuing without requiring per flow state information at the router.

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaves 139-142. / by Michael Gene Hluchyj. / Ph.D.

Thesis (Elec.E)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Michael Gene Hluchyj. / Elec.E

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1978. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Bibliography: leaf 58. / B.S.