In this research we consider developing a reservoir simulator capable of simulating complex coupled poromechanical processes on massively parallel computers. A variety of problems arising from petroleum and environmental engineering inherently necessitate the understanding of interactions between fluid flow and solid mechanics. Examples in petroleum engineering include reservoir compaction, wellbore collapse, sand production, and hydraulic fracturing. In environmental engineering, surface subsidence, carbon sequestration, and waste disposal are also coupled poromechanical processes. These economically and environmentally important problems motivate the active pursuit of robust, efficient, and accurate simulation tools for coupled poromechanical problems. Three coupling approaches are currently employed in the reservoir simulation community to solve the poromechanics system, namely, the fully implicit coupling (FIM), the explicit coupling, and the iterative coupling. The choice of the coupling scheme significantly affects the efficiency of the simulator and the accuracy of the solution. We adopt the fixed-stress iterative coupling scheme to solve the coupled system due to its advantages over the other two. Unlike the explicit coupling, the fixed-stress split has been theoretically proven to converge to the FIM for linear poroelasticity model. In addition, it is more efficient and easier to implement than the FIM. Our computational results indicate that this approach is also valid for multiphase flow. We discretize the quasi-static linear elasticity model for geomechanics in space using the continuous Galerkin (CG) finite element method (FEM) on general hexahedral grids. Fluid flow models are discretized by locally mass conservative schemes, specifically, the mixed finite element method (MFE) for the equation of state compositional flow on Cartesian grids and the multipoint flux mixed finite element method (MFMFE) for the single phase and two-phase flows on general hexahedral grids. While both the MFE and the MFMFE generate cell-centered stencils for pressure, the MFMFE has advantages in handling full tensor permeabilities and general geometry and boundary conditions. The MFMFE also obtains accurate fluxes at cell interfaces. These characteristics enable the simulation of more practical problems. For many reservoir simulation applications, for instance, the carbon sequestration simulation, we need to account for thermal effects on the compositional flow phase behavior and the solid structure stress evolution. We explicitly couple the poromechanics equations to a simplified energy conservation equation. A time-split scheme is used to solve heat convection and conduction successively. For the convection equation, a higher order Godunov method is employed to capture the sharp temperature front; for the conduction equation, the MFE is utilized. Simulations of coupled poromechanical or thermoporomechanical processes in field scales with high resolution usually require parallel computing capabilities. The flow models, the geomechanics model, and the thermodynamics model are modularized in the Integrated Parallel Accurate Reservoir Simulator (IPARS) which has been developed at the Center for Subsurface Modeling at the University of Texas at Austin. The IPARS framework handles structured (logically rectangular) grids and was originally designed for element-based data communication, such as the pressure data in the flow models. To parallelize the node-based geomechanics model, we enhance the capabilities of the IPARS framework for node-based data communication. Because the geomechanics linear system is more costly to solve than those of flow and thermodynamics models, the performance of linear solvers for the geomechanics model largely dictates the speed and scalability of the coupled simulator. We use the generalized minimal residual (GMRES) solver with the BoomerAMG preconditioner from the hypre library and the geometric multigrid (GMG) solver from the UG4 software toolbox to solve the geomechanics linear system. Additionally, the multilevel k-way mesh partitioning algorithm from METIS is used to generate high quality mesh partitioning to improve solver performance. Numerical examples of coupled poromechanics and thermoporomechanics simulations are presented to show the capabilities of the coupled simulator in solving practical problems accurately and efficiently. These examples include a real carbon sequestration field case with stress-dependent permeability, a synthetic thermoporoelastic reservoir simulation, poroelasticity simulations on highly distorted hexahedral grids, and parallel scalability tests on a massively parallel computer. / text

Thesis (M.C.S.)--Miami University, Dept. of Computer Science and Systems Analysis, 2009. / Title from first page of PDF document. Includes bibliographical references (p. 72-75).

Les systèmes HPC ("High-Performance Computing") sont des systèmes conçus avec des centaines de milliers de nœuds de calcul interconnectés entre eux par un réseau de communication de haute performance, lui-même assemblé suivant une variété de topologie par des nœuds de routage. La conception du réseau d'interconnexion d'un système HPC revêt une importance capitale dans la performance finale du système. La complexité de cette conception requiert la mise en œuvre d'un environnement de prototypage virtuel afin de pouvoir analyser et valider les hypothèses et options micro et macro-architecturales dès les premières étapes de la conception. Les travaux de cette thèse sont dédiés au développement d'une plate-forme de prototypage virtuel nommée CoSIN ("Composition and Simulation of Interconnected Network") pour assister les architectes de la société Bull S.A.S. dans leur conception des systèmes HPC. Ces travaux répondent au défi de modélisation et de simulation de réseaux de très grand taille (de 10^4 à 10^5 nœuds) et ce en des temps acceptables. Pour ce faire, l'environnement de programmation SystemC a été mis en parallèle afin de fournir une puissance de calcul et une capacité de mémoire distribuées. En plus de l'aspect conceptuel, a thèse se veut aussi pragmatique en produisant comme résultat, un outil déjà applicable à des projets de conception industriels / High-Performance Computing (HPC) systems are distributed systems made of hundreds of thousands of processing nodes communicating through large packet-switched interconnection networks with a variety of topologies. The design of those interconnection networks impacts the overall performance of the HPC systems. Due to increasing system complexity, virtual prototyping is becoming necessary at earlier stages of the design to assist in the analysis and validation of micro and macro-architectural hypotheses and options. This thesis is dedicated to the development of such a virtual prototyping framework named CoSIN ("Composition and Simulation of Interconnected Network") with the purpose of providing support to the architectural design of HPC systems at Bull S.A.S. Technical challenges of the work are in the modelling and simulation of large interconnection networks (from 10^4 to 10^5 nodes) within acceptable times. Distribution of SystemC has been necessary to support this objective. In addition to the conceptual aspect, the thesis is also pragmatic by producing as results, a tool already applicable to industrial design projects

In a heterogeneous mobile ad hoc network (MANET), assorted devices with different computation and communication capabilities co-exist. In this thesis, we consider the case when the nodes of a MANET have various degrees of mobility and range, and the communication links are asymmetric. Many routing protocols for ad hoc networks routinely assume that all communication links are symmetric, if node A can hear node B and node B can also hear node A. Most current MAC layer protocols are unable to exploit the asymmetric links present in a network, thus leading to an inefficient overall bandwidth utilization, or, in the worst case, to lack of connectivity. To exploit the asymmetric links, the protocols must deal with the asymmetry of the path from a source node to a destination node which affects either the delivery of the original packets, or the paths taken by acknowledgments, or both. Furthermore, the problem of hidden nodes requires a more careful analysis in the case of asymmetric links. MAC layer and routing protocols for ad hoc networks with asymmetric links require a rigorous performance analysis. Analytical models are usually unable to provide even approximate solutions to questions such as end-to-end delay, packet loss ratio, throughput, etc. Traditional simulation techniques for large-scale wireless networks require vast amounts of storage and computing cycles rarely available on single computing systems. In our search for an effective solution to study the performance of wireless networks we investigate the time-parallel simulation. Time-parallel simulation has received significant attention in the past. The advantages, as well as, the theoretical and practical limitations of time-parallel simulation have been extensively researched for many applications when the complexity of the models involved severely limits the applicability of analytical studies and is unfeasible with traditional simulation techniques. Our goal is to study the behavior of large systems consisting of possibly thousands of nodes over extended periods of time and obtain results efficiently, and time-parallel simulation enables us to achieve this objective. We conclude that MAC layer and routing protocols capable of using asymmetric links are more complex than traditional ones, but can improve the connectivity, and provide better performance. We are confident that approximate results for various performance metrics of wireless networks obtained using time-parallel simulation are sufficiently accurate and able to provide the necessary insight into the inner workings of the protocols.

Avec la complexité croissante des systèmes sur puce, de nouveaux défis ne cessent d’émerger dans la conception de ces systèmes en matière de vérification formelle et de synthèse de haut niveau. Plusieurs travaux autour de SystemC, considéré comme la norme pour la conception au niveau système, sont en cours afin de relever ces nouveaux défis. Cependant, à cause du modèle de concurrence complexe de SystemC, relever ces défis reste toujours une tâche difficile. Ainsi, nous pensons qu’il est primordial de partir sur de meilleures bases en utilisant un modèle de concurrence plus efficace. Par conséquent, dans cette thèse, nous étudions une méthodologie de conception qui offre une meilleure abstraction pour modéliser des composants parallèles en se basant sur le concept de transaction. Nous montrons comment, grâce au raisonnement simple que procure le concept de transaction, il devient plus facile d’appliquer la vérification formelle, le raffinement incrémental et la synthèse de haut niveau. Dans le but d’évaluer l’efficacité de cette méthodologie, nous avons fixé l’objectif d’optimiser la vitesse de simulation d’un modèle transactionnel en profitant d’une machine multicoeur. Nous présentons ainsi l’environnement de modélisation et de simulation parallèle que nous avons développé. Nous étudions différentes stratégies d’ordonnancement en matière de parallélisme et de surcoût de synchronisation. Une expérimentation faite sur un modèle du transmetteur Wi-Fi 802.11a a permis d’atteindre une accélération d’environ 1.8 en utilisant deux threads. Avec 8 threads, bien que la charge de travail des différentes transactions n’était pas importante, nous avons pu atteindre une accélération d’environ 4.6, ce qui est un résultat très prometteur. / With the increasing complexity of SoCs, new challenges continue to emerge in the design of these systems in terms of formal verification and high-level synthesis. Several research efforts around SystemC, considered the de facto standard for system-level design, are underway to meet these new challenges. However, because of the complex concurrency model of SystemC, these challenges remain difficult tasks. Thus, we believe it is important to continue on a better footing by using a more effective concurrency model. Therefore, in this thesis, we study a design methodology that provides a better abstraction for modeling parallel components based on the concept of transaction. We show how, through simple reasoning about transactions, it becomes easier to apply formal verification, incremental refinement and high-level synthesis. In order to evaluate the effectiveness of this methodology, we set the goal to optimize the simulation speed of a transactional model by taking advantage of a multicore machine. We present a modeling and parallel simulation environment that we developed. We study different scheduling strategies in terms of parallelism and synchronization overhead. An experiment made on a Wi-Fi 802.11a transmitter model achieved a speed up of about 1.8 using two threads. With 8 threads, although the workload of individual transactions was not significant, we could reach a speed up equal to 4.6 which is a very promising result.

Vor allem bei der Betrachtung großer und komplexer Szenarien ist eine Kombination der Vorteile der sequentiellen und parallelen Simulationswelten wünschenswert. Derartige Szenarien lassen sich meist nur bei einer adäquaten, strukturäquivalenten Modellierung, wie in der sequentiellen Simulationswelt üblich, beherrschen. Es sind aber auch gleichzeitig genau diese Simulationsszenarien, die auch am ehesten nach einer Beschleunigung der Simulationsausführung, z.B. durch eine Parallelisierung, verlangen. Die vorliegende Arbeit beschreibt die Konzeption und Implementation einer optimistisch-parallelen Simulationsbibliothek in Java. Diese vereint die Vorzüge optimistisch-paralleler Simulation (automatische Ausnutzung modellinhärenter Parallelität zur Simulationsbeschleunigung) mit der des prozessorientierten Paradigmas (modellabhängig strukturäquivalente und intuitive Modellbeschreibungen). Eine Implementation des prozessorientierten Paradigmas in einer parallelen Simulation ist allerdings nicht unproblematisch. Dies gilt vor allem im Spezialfall der optimistisch-parallelen Simulation, die sich dadurch auszeichnet, dass Simulationsmodelle während eines Simulationslaufes in ungültige Zustände geraten können, was jeweils durch eine Rückkehr des Simulationsmodells in einen früheren, korrekten Zustand korrigiert wird. Ein weiteres Entwicklungsziel besteht darin, im Gegensatz zu den meisten existierenden PDES-Implementationen die interne Arbeitsweise des optimistisch-parallelen Simulationskerns so gut wie möglich zu verbergen. Stattdessen gleichen die vom Simulationskern angebotenen Schnittstellen weitestgehend denen von sequentiellen Simulationskernen. Dadurch wird die Erstellung eines passenden Simulationsmodells im Vergleich zu anderen parallelen Simulationsimplementationen deutlich erleichtert. Auch der Mehraufwand gegenüber der Erstellung von Simulationsmodellen für rein sequentielle Simulationskerne ist relativ gering. / A combination of the advantages of the sequential, as well as the parallel simulation approach is desirable, especially in the case of large and complex simulation scenarios. These are only manageable if a corresponding structurally equivalent simulation model is employed. Also, the very same models will profit most from a speed-up by parallelization. Unfortunately, the implementation of a process-oriented view in a parallel fashion is not a trivial task. Parallel simulation implementations generally suffer from additional computational cost that can offset the parallel speed-up and even lead to a diminished parallel performance, which is even more likely to happen when using process-oriented simulation models. This is especially the case in optimistic-parallel simulations. These are characterized by the ability of the model to get into invalid states which is costly being corrected at runtime by returning the model to valid former states preliminarily saved. The aim of this thesis is the design and implementation of a simulation library in Java. It combines the advantages of optimistic-parallel simulation (i.e. use of parallelism for speed-up) and the process-oriented modeling (creation of an intuitive and structurally equivalent model). Another central objective of the development is to hide the internals of the optimistic-parallel simulation kernel from the modeler, in contrast to most existing PDES implementations. Instead, the implementation is encapsulated by interfaces, which resemble those of sequential simulation kernels, reducing the additional effort needed to create a suited model. A noteworthy aspect of the implementation is the reuse of a web application framework for retroactive modification of the Java bytecode, generated by the Java compiler. This bytecode rewriting solves in an elegant way the task of realizing coroutines, which are the base for the implementation of processes as needed by process-oriented simulation models.

Avec la complexité croissante des systèmes sur puce, de nouveaux défis ne cessent d’émerger dans la conception de ces systèmes en matière de vérification formelle et de synthèse de haut niveau. Plusieurs travaux autour de SystemC, considéré comme la norme pour la conception au niveau système, sont en cours afin de relever ces nouveaux défis. Cependant, à cause du modèle de concurrence complexe de SystemC, relever ces défis reste toujours une tâche difficile. Ainsi, nous pensons qu’il est primordial de partir sur de meilleures bases en utilisant un modèle de concurrence plus efficace. Par conséquent, dans cette thèse, nous étudions une méthodologie de conception qui offre une meilleure abstraction pour modéliser des composants parallèles en se basant sur le concept de transaction. Nous montrons comment, grâce au raisonnement simple que procure le concept de transaction, il devient plus facile d’appliquer la vérification formelle, le raffinement incrémental et la synthèse de haut niveau. Dans le but d’évaluer l’efficacité de cette méthodologie, nous avons fixé l’objectif d’optimiser la vitesse de simulation d’un modèle transactionnel en profitant d’une machine multicoeur. Nous présentons ainsi l’environnement de modélisation et de simulation parallèle que nous avons développé. Nous étudions différentes stratégies d’ordonnancement en matière de parallélisme et de surcoût de synchronisation. Une expérimentation faite sur un modèle du transmetteur Wi-Fi 802.11a a permis d’atteindre une accélération d’environ 1.8 en utilisant deux threads. Avec 8 threads, bien que la charge de travail des différentes transactions n’était pas importante, nous avons pu atteindre une accélération d’environ 4.6, ce qui est un résultat très prometteur. / With the increasing complexity of SoCs, new challenges continue to emerge in the design of these systems in terms of formal verification and high-level synthesis. Several research efforts around SystemC, considered the de facto standard for system-level design, are underway to meet these new challenges. However, because of the complex concurrency model of SystemC, these challenges remain difficult tasks. Thus, we believe it is important to continue on a better footing by using a more effective concurrency model. Therefore, in this thesis, we study a design methodology that provides a better abstraction for modeling parallel components based on the concept of transaction. We show how, through simple reasoning about transactions, it becomes easier to apply formal verification, incremental refinement and high-level synthesis. In order to evaluate the effectiveness of this methodology, we set the goal to optimize the simulation speed of a transactional model by taking advantage of a multicore machine. We present a modeling and parallel simulation environment that we developed. We study different scheduling strategies in terms of parallelism and synchronization overhead. An experiment made on a Wi-Fi 802.11a transmitter model achieved a speed up of about 1.8 using two threads. With 8 threads, although the workload of individual transactions was not significant, we could reach a speed up equal to 4.6 which is a very promising result.

Radio access technologies for cellular mobile networks are continuously being evolved to meet the future demands for higher data rates, and lower end‐to‐end delays. In the research and development of LTE, radio network simulations play an essential role. The evolution of parallel processing hardware makes it desirable to exploit the potential gains of parallelizing LTE radio network simulations using multithreading techniques in contrast to distributing experiments over processors as independent simulation job processes. There is a hypothesis that parallel speedup gain diminishes when running many parallel simulation jobs concurrently on the same machine due to the increased memory requirements. A proposed multithreaded prototype of the Ericsson LTE simulator has been constructed, encapsulating scheduling, execution and synchronization of asynchronous physical layer computations. In order to provide implementation transparency, an algorithm has been proposed to sort and synchronize log events enabling a sequential logging model on top of non‐deterministic execution. In order to evaluate and compare multithreading techniques to parallel simulation job distribution, a large number of experiments have been carried out for four very diverse simulation scenarios. The evaluation of the results from these experiments involved analysis of average measured execution times and comparison with ideal estimates derived from Amdahl’s law in order to analyze overhead. It has been shown that the proposed multithreaded task‐oriented framework provides a convenient way to execute LTE physical layer models asynchronously on multi‐core processors, still providing deterministic results that are equivalent to the results of a sequential simulator. However, it has been indicated that distributing parallel independent jobs over processors is currently more efficient than multithreading techniques, even though the achieved speedup is far from ideal. This conclusion is based on the observation that the overhead caused by increased memory requirements, memory access and system bus congestion is currently smaller than the thread management and synchronization overhead of the proposed multithreaded Java prototype.

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