Low-density parity-check (LDPC) codes are linear error correcting codes which are capable of performing near channel capacity. Furthermore, they admit efficient decoding algorithms that provide near optimum performance. Their main disadvantage is that most LDPC codes have relatively complex encoders. In this thesis, we begin by giving a detailed discussion of the sum-product decoding algorithm, we then study the performance of LDPC codes on the binary erasure channel under sum-product decoding to obtain criteria for the design of codes that allow reliable transmission at rates arbitrarily close to channel capacity. Using these criteria we show how such codes are designed. We then present experimental results and compare them with theoretical predictions. Finally, we provide an overview of several approaches to solving the complex encoder problem.

In this thesis, we extend applications of Low-Density Parity-Check (LDPC) codes to a combination of constituent sub-channels, which is a mixture of Gaussian channels with erasures. This model, for example, represents a common channel in magnetic recordings where thermal asperities in the system are detected and represented at the decoder as erasures. Although this channel is practically useful, we cannot find any previous work that evaluates performance of LDPC codes over this channel. We are also interested in practical issues such as designing robust LDPC codes for the mixture channel and predicting performance variations due to erasure patterns (random and burst), and finite block lengths. On time varying channels, a common error control strategy is to adapt the coding rate according to available channel state information (CSI). An effective way to realize this coding strategy is to use a single code and puncture it in a rate-compatible fashion, a so-called rate-compatible punctured code (RCPC). We are interested in the existence of good puncturing patterns for rate-changes that minimize performance loss. We show the existence of good puncturing patterns with analysis and verify the results with simulations. Universality of a channel code across a broad range of coding rates is a theoretically interesting topic. We are interested in the possibility of using the puncturing technique proposed in this thesis for designing universal LDPC codes. We also consider how to design high rate LDPC codes by puncturing low rate LDPC codes. The new design method can take advantage of longer effect block lengths, sparser parity-check matrices, and larger minimum distances of low rate LDPC codes.

Among the recent advances in the area of low-density parity-check (LDPC) codes, protograph-based LDPC codes have the advantages of a simple design procedure and highly structured encoders and decoders. These advantages can also be exploited in the design of protograph-based generalized LDPC (G-LDPC) codes. In this dissertation we provide analytical tools which aid the design of protograph-based LDPC and G-LDPC codes. Specifically, we propose a method for computing the codeword-weight enumerators for finite-length protograph-based G-LDPC code ensembles, and then we consider the asymptotic case when the block-length goes to infinity. These results help the designer identify good ensembles of protograph-based G-LDPC codes in the minimum distance sense (i.e., ensembles which have minimum distances grow linearly with code length). Furthermore, good code ensembles can be characterized by good stopping set, trapping set, or pseudocodeword properties, which assist in the design of G-LDPC codes with low floors. We leverage our method for computing codeword-weight enumerators to compute stopping-set, and pseudocodeword enumerators for the finite-length and the asymptotic ensembles of protograph-based G-LDPC codes. Moreover, we introduce a method for computing trapping set enumerators for finite-length (and asymptotic) protograph-based LDPC code ensembles. Trapping set enumerators for G-LDPC codes represents a more complex problem which we do not consider here. Inspired by our method for computing trapping set enumerators for protograph-based LDPC code ensembles, we developed an algorithm for estimating the trapping set enumerators for a specific LDPC code given its parity-check matrix. We used this algorithm to enumerate trapping sets for several LDPC codes from communication standards. Finally, we study coded-modulation schemes with LDPC codes and pulse position modulation (LDPC-PPM) over the free-space optical channel. We present three different decoding schemes and compare their performances. In addition, we developed a new density evolution tool for use in the design of LDPC codes with good performances over this channel.

In mobile communication, the user’s information is transmitted through a wireless communication link that is subjected to a range of deteriorating effects. The quality of the transmission can be presented by the rate of transfer and the reliability of the received stream. The capacity of the communication link can be reached through the use of channel coding. Channel coding is the method of adding redundant information to the user’s information to mitigate the deteriorating effects of the communication link. Mobile WiMAX is a technology that makes use of orthogonal frequency division multiplexing (OFDM) modulation to transmit information over a wireless communication channel. The OFDM physical layer has a high peak average to power ratio (PAPR) characteristic that saturates the transmitter’s amplifier quite easily when proper backoff is not made in the transmission power. In this dissertation an optimized graph code was used as an alternative solution to improve the system’s performance in the presence of a saturated transmission’s amplifier. The graph code was derived from a degree distribution given by the density evolution algorithm and provided no extra network overhead to implement. The performance analysis resulted in a factor of 10 improvement in the error floor and a coding gain of 1.5 dB. This was all accomplished with impairments provided by the mobile WiMAX standard in the construction of the graph code. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted

A new computing platform, the General Purpose Reprsentation and Association Machine is studied and simulated. GPRAM machines use vague measurements to do a quick and rough assessment on a task; then use approximated message-passing algorithms to improve assessment; and finally selects ways closer to a solution, eventually solving it. We illustrate concepts and structures using simple examples.

Window decoding schedules are very attractive for message passing decoding of spatially coupled LDPC codes. They take advantage of the inherent convolutional code structure and allow continuous transmission with low decoding latency and complexity. In this paper we show that the decoding complexity can be further reduced if suitable message passing schedules are applied within the decoding window. An improvement based schedule is presented that easily adapts to different ensemble structures, window sizes, and channel parameters. Its combination with a serial (on-demand) schedule is also considered. Results from a computer search based schedule are shown for comparison.

Current coherent optical transmission systems focus on single carrier solutions for 400Gb/s serial transmission to support traffic growth in fiber-optics communications, together with a few subcarriers multiplexed solutions for the 1 Tb/s serial data rates and beyond. With the advancement of analog-to-digital converter technologies, high order modulation formats up to 64-QAM with symbol rate up to 72Gbaud have been demonstrated experimentally with Raman amplification. To enable such high serial data rates, it is highly desirable to implement in hardware low complexity digital signal processing schemes and advanced forward error correction coding with powerful error correction capability. In this dissertation, to enable high-speed optical communications, we first proposed an efficient FPGA architecture of high-performance binary and non-binary LDPC engines that can support throughputs of multiple Gb/s, which have low power consumption, providing high net coding gains at a target bit-error rate of 10-15. Further, we implement a generalized LDPC coding based rate adaptive binary LDPC coding scheme and puncturing based rate adaptive non-binary LDPC coding scheme, where large number of parameters can be reconfigured in order to cope with the time-varying optical channel conditions and service requirements. Based on comprehensive analysis on complexity, latency, and power consumption we demonstrate that the proposed efficient implementation represents a feasible solution for the next generation optical communication networks. Additionally, we investigate the FPGA implementation of rate adaptive regular LDPC coding combined with up to six high-order modulation formats and demonstrate high net coding gain performance and demonstrated a bit loading algorithm for irregular LDPC coding. Lastly, we present the real-time implementation of a direct detection OFDM transceiver with multi Giga symbols/s symbol rates in a back-to-back configuration.

In wireless communications, the use of multiple antennas at both the transmitter and the receiver is a key technology to enable high data rate transmission without additional bandwidth or transmit power. Multiple-input multiple-output (MIMO) schemes are widely used in many wireless standards, allowing higher throughput using spatial multiplexing techniques. MIMO soft detection poses significant challenges to the MIMO receiver design as the detection complexity increases exponentially with the number of antennas. As the next generation wireless system is pushing for multi-Gbps data rate, there is a great need for high-throughput low-complexity soft-output MIMO detector. The brute-force implementation of the optimal MIMO detection algorithm would consume enormous power and is not feasible for the current technology. We propose a reduced-complexity soft-output MIMO detector architecture based on a trellis-search method. We convert the MIMO detection problem into a shortest path problem. We introduce a path reduction and a path extension algorithm to reduce the search complexity while still maintaining sufficient soft information values for the detection. We avoid the missing counter-hypothesis problem by keeping multiple paths during the trellis search process. The proposed trellis-search algorithm is a data-parallel algorithm and is very suitable for high speed VLSI implementation. Compared with the conventional tree-search based detectors, the proposed trellis-based detector has a significant improvement in terms of detection throughput and area efficiency. The proposed MIMO detector has great potential to be applied for the next generation Gbps wireless systems by achieving very high throughput and good error performance. The soft information generated by the MIMO detector will be processed by a channel decoder, e.g. a low-density parity-check (LDPC) decoder or a Turbo decoder, to recover the original information bits. Channel decoder is another very computational-intensive block in a MIMO receiver SoC (system-on-chip). We will present high-performance LDPC decoder architectures and Turbo decoder architectures to achieve 1+ Gbps data rate. Further, a configurable decoder architecture that can be dynamically reconfigured to support both LDPC codes and Turbo codes is developed to support multiple 3G/4G wireless standards. We will present ASIC and FPGA implementation results of various MIMO detectors, LDPC decoders, and Turbo decoders. We will discuss in details the computational complexity and the throughput performance of these detectors and decoders.

In this thesis, we present a space-time coded system which achieves high through- put and good performance with low processing delay using low-complexity detection and decoding. Initially, Hamming codes are used in a simple interleaved bit-mapped coded modulation structure (BMCM). This is concatenated with Alamouti's or- thogonal space-time block codes. The good performance achieved by this system indicates that higher throughput is possible while maintaining performance. An analytical bound for the performance of this system is presented. We also develop a class of low density parity check codes which allows flexible "throughput versus performance" tradeoffs. We then focus on a Rate 2 quasi-orthogonal space-time block code structure which enables us to achieve an overall throughput of 5.6 bits/symbol period with good performance and relatively simple decoding using iterative parallel interference cancellation. We show that this can be achieved through the use of a bit-mapped coded modulation structure using parallel short low density parity check codes. The absence of interleavers here reduces processing delay significantly. The proposed system is shown to perform well on flat Rayleigh fading channels with a wide range of normalized fade rates, and to be robust to channel estimation errors. A comparison with bit-interleaved coded modulation is also provided (BICM).

Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on Field-Programmable Gate Array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a digit-online decoder depends on various factors, like input log-likelihood ratio (LLR) bit precision, signal-to-noise ratio (SNR) and maximum number of iterations. The design is implemented on an Altera Stratix IV GX EP4SGX230 FPGA, which comes on an Altera DE4 Development and Education Board. In this work, both parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit, rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a random-data generator, WiMAX Encoder, shift-out register, additive white Gaussian noise (AWGN) generator, channel LLR buffer, WiMAX Decoder and bit-error rate (BER) Calculator. The random-data generator outputs pseudo-random bit patterns through an implemented linear-feedback shift register (LFSR). Digit-online decoders with input LLR precisions ranging from 6 to 13 bits and parallel decoders with input LLR precisions ranging from 3 to 6 bits are synthesized in a Stratix IV FPGA. The digit-online decoders can be clocked at higher frequency for higher LLR precisions. A digit-online decoder can be used to decode two frames simultaneously in frame-interlaced mode. For the 6-bit implementation of digit-online decoder in single-frame mode, the minimum throughput achieved is 740 Mb/s at low SNRs. For the case of 11-bit LLR digit-online decoder in frame-interlaced mode, the minimum throughput achieved is 1363 Mb/s. Detailed analysis such as effect of SNR and LLR precision on decoder power is presented. Also, the effect of changing LLR precision on max clock frequency and logic utilization on the parallel and the digit-online decoders is studied. Alongside, power per iteration for a 6-bit LLR input digit-online decoder is also reported.