Network coding is a promising technology that many researchers have advocated due to its potentially significant benefits to improve the efficiency of data transmission. In this thesis, we use simulations to evaluate the performance of different network topologies using network coding. By comparing the results with networks without network coding, we confirm that network coding can improve the network throughput. It also has a potential to decrease the end to end delay and improve the reliability. However, there are tradeoff (between delay and reliability) when network coding is used, and some limitations which we summarize. Finally, we have also implemented network coding to a three-dimensional underwater network by using parameters that truly reflect the underwater channel. Our performance evaluations show a better throughput and end-to-end delay but not the PDR (Packet Delivery Rate) in the underwater topology we used.

The popularity of Amazon's EC2 cloud platform has increased in commercial and scientific high-performance computing (HPC) applications domain in recent years. However, many HPC users consider dedicated high-performance clusters, typically found in large compute centers such as those in national laboratories, to be far superior to EC2 because of significant communication overhead of the latter. We find this view to be quite narrow and the proper metrics for comparing high-performance clusters to EC2 is turnaround time and cost. In this work, we first compare the HPC-grade EC2 cluster to top-of-the-line HPC clusters based on turnaround time and total cost of execution. When measuring turnaround time, we include expected queue wait time on HPC clusters. Our results show that although as expected, standard HPC clusters are superior in raw performance, they suffer from potentially significant queue wait times. We show that EC2 clusters may produce better turnaround times due to typically lower wait queue times. To estimate cost, we developed a pricing model---relative to EC2's node-hour prices---to set node-hour prices for (currently free) HPC clusters. We observe that the cost-effectiveness of running an application on a cluster depends on raw performance and application scalability. However, despite the potentially lower queue wait and turnaround times, the primary barrier to using clouds for many HPC users is the cost. Amazon EC2 provides a fixed-cost option (called on-demand) and a variable-cost, auction-based option (called the spot market). The spot market trades lower cost for potential interruptions that necessitate checkpointing; if the market price exceeds the bid price, a node is taken away from the user without warning. We explore techniques to maximize performance per dollar given a time constraint within which an application must complete. Specifically, we design and implement multiple techniques to reduce expected cost by exploiting redundancy in the EC2 spot market. We then design an adaptive algorithm that selects a scheduling algorithm and determines the bid price. We show that our adaptive algorithm executes programs up to 7x cheaper than using the on-demand market and up to 44% cheaper than the best non-redundant, spot-market algorithm. Finally, we extend our adaptive algorithm to exploit several opportunities for cost-savings on the EC2 spot market. First, we incorporate application scalability characteristics into our adaptive policy. We show that the adaptive algorithm informed with scalability characteristics of applications achieves up to 56% cost-savings compared to the expected cost for the base adaptive algorithm run at a fixed, user-defined scale. Second, we demonstrate potential for obtaining considerable free computation time on the spot market enabled by its hour-boundary pricing model.

La course à la miniaturisation des circuits électroniques pousse à développer des systèmes faible coût, quece soit en terme de consommation d’énergie ou de ressources de calcul. Il est ainsi possible de réduire la consommationen diminuant la tension d’alimentation et/ou la fréquence d’horloge, mais ceci a pour conséquence de diminuer aussila vitesse de fonctionnement du circuit. Une commande prédictive rapide permet alors de gérer dynamiquement un telcompromis, de manière à ce que la consommation d’énergie soit minimisée tout en garantissant de bonnes performances.Les stratégies de commande proposées ont notamment l’avantage d’être très robustes aux dispersions technologiquesqui sont un problème récurrent dans les nanopuces. Des solutions sont également proposées afin de réduire le coût decalcul du contrôleur. Les systèmes à échantillonnage non-uniforme, dont la loi de commande est calculée et mise à jourlorsqu’un événement est déclenché, sont ainsi étudiés. Ce principe permet de réduire le nombre d’échantillons et, parconséquent, d’économiser des ressources de calcul, tout en garantissant de bonnes performances du système commandé.Des résultats de simulation, et surtout expérimentaux, valident finalement l’intérêt d’utiliser une telle approche. / The demand of electronic components in all embedded and miniaturized applications encourages to developlow-cost components, in term of energy consumption and computational resources. Actually, the power consumption canbe reduced when decreasing the supply voltage and/or the clock frequency, but with the effect that the device runs moreslowly in return. Nevertheless, a fast predictive control strategy allows to dynamically manage this tradeoff in order tominimize the energy consumption while ensuring good performance of the device. Furthermore, the proposals are highlyrobust to tackle variability which is a real problem in nanometric systems on chip. Some issues are also suggested inthis thesis to reduce the control computational cost. Contrary to a time-triggered system where the controller calculatesthe control law at each (constant and periodic) sampling time, an event-based controller updates the control signalonly when the measurement sufficiently changes. Such a paradigm hence calls for resources whenever they are indeednecessary, that is when required from a performance or stability point of view for instance. The idea is to soften thecomputational load by reducing the number of samples and consequently the CPU utilization. Some simulation andexperimental results eventually validate the interest of such an approach.

Proportional, integral and derivative (PID) controller tuning guidelines in process industry have been in place for over six decades. Nevertheless despite their long design history PID tuning has remained an ‘art’ and no single comprehensive solution yet exists. In this study various considerations, with new and different perspectives, have been taken into account in PID tuning design. This study explores the issue of PID tuning from a practical point of view with particular focus on robust design in the presence of typical problems in process industry: process changes, valve stiction effects and unmeasured disturbances. The IMC tuning rule is recommended for setpoint tracking, while in the case of regulation, a newly proposed tuning rule, based on a combination of IMC and Ziegler-Nichols method, is demonstrated to give satisfactory results. The results were evaluated by simulation and were also validated on a computer-interfaced pilot scale continuous stirred tank heater (CSTH) process. / Chemical Engineering

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

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