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The characteristics of a Zinc/Air (Zn/Air) primary cell are discussed. In addition, current technologies and the corresponding electrical performance are introduced. The basic principles of operation of a Zn/Air primary cell are discussed, focusing on the anode, cathode, and electrolyte. Basic kinetic and transport expressions are developed for the two main components of the cell: the anode and cathode compartments, based on which an overall formula for the cell polarization is developed. Input parameters are selected and approximated where possible to observe the model¡¦s ability to predict potential versus current density. Time-dependent anode performance is accomplished through the use of the shrinking core reaction model for the discharge of the zinc particles. The time-dependent dimensionless radius of the zinc particle (ď) is then used in conjunction with the developed transport and kinetic expressions for the prediction of the overall cell performance as a function of time. Plots of cell voltage prediction versus time and percent capacity versus time are presented. The simulations indicate an adequate approximate analytic model valid for a variety of drain rates corresponding to current hearing instrument devices in the market.

Las aplicaciones paralelas presentan diversos problemas de prestaciones al ser cambiadas para ejecutar en entornos Grid. Las características del sistema pueden ser diferentes en cada ejecución y en algunos casos dentro de una misma ejecución. Los recursos remotos comparten enlaces de red y, los procesos de la aplicación comparten las maquinas con otros procesos. En esos escenarios se propone el uso de la técnica de sintonización dinámica de prestaciones para ayudar las aplicaciones a adaptarse a los cambios en las características del sistema con la intención de resolver los problemas de prestaciones. Esta tesis analiza el problema de la ejecución de aplicaciones paralelas en entornos Grid, herramientas para el análisis de prestaciones disponibles y modelos adecuados para la sintonización dinámica de aplicaciones paralelas en este tipo de entorno. De este análisis, se propone una arquitectura para sintonización dinámica de aplicaciones paralelas en entornos Grid llamada GMATE. Esta arquitectura incluye diversas contribuciones. En el caso donde un gestor de recursos de alto nivel decide el mapeo de procesos de la aplicación, se proponen dos aproximaciones para el seguimiento de procesos que habilita GMATE a localizar donde las capas de software del Grid ha mapeado los procesos de la aplicación. Una aproximación consiste en la integración de GMATE a las capas de software del Grid. La otra integra los componentes requeridos de GMATE dentro de los binarios de la aplicación. El primer enfoque requiere derechos de administración en cuanto que el segundo incrementa el binario del la aplicación, lo que torna más lento el arranque de la misma. Para respetar las políticas de las organizaciones propietarias de los recursos, todas las comunicaciones usan el mismo certificado de seguridad de la aplicación. Esas comunicaciones son hechas con base en las capas del Grid. Esta aproximación habilita la arquitectura a monitorizar y sintonizar los procesos de la aplicación de forma dinámica a las restricciones de cortafuegos de las organizaciones y políticas de uso de la red en las mismas. Para bajar la necesidad de comunicaciones en la arquitectura GMATE, se encapsula parte de la lógica requerida para colectar las medidas y para cambiar los parámetros de la aplicación en componentes encuestados que ejecutan dentro de espacio de memoria del proceso de la aplicación. Para colectar medidas, se ha creado componentes sensores que disminuyen la necesidad de comunicaciones llevando el procesamiento de eventos para dentro del proceso de la aplicación. Diferente de la instrumentación tradicional, los sensores pueden retrasar la transmisión de los eventos y ejecutar operaciones básicas como sumas, temporizadores, promedios o generación de eventos basados en umbrales. Esas capacidades reducen los requerimientos de comunicaciones que son útiles en situaciones de bajo ancho de banda. Se propone también el encapsulamiento de la lógica de cambio en las aplicaciones en componentes actuadores. Los actuadores son instalados en el flujo de ejecución de la aplicación y posibilita la sincronización y baja intrusión en cambio de variables y ejecución de funciones para modificar la aplicación. La arquitectura propuesta posibilita la comunicación entre sensores y actuadores lo cual habilita la sintonizaciones sencillas sin necesidad de comunicaciones. Para aplicar la sintonización dinámica en entornos Grid, necesitamos de un modelo de prestaciones que pueda ser usado en entornos con heterogeneidad de red y procesadores para guiar el proceso. Se propone un modelo de prestaciones basado en una heurística para lograr usar el máximo número de esclavos y el mejor tamaño de grano en una ejecución Maestro-Esclavo en sistemas Grid. Se considera que una clase de aplicaciones pueden ser desarrolladas con la capacidad de cambiar el tamaño de grano en tiempo de ejecución y que esa acción cambia la relación entre cómputo y comunicación. En el escenario donde usuarios reciben un conjunto de recursos para una ejecución paralela, esos recursos pueden configurar un sistema de múltiples clústeres. La heurística del modelo presentado permite guiar la selección de los recursos para disminuir el tiempo total de ejecución de la aplicación. Se intenta buscar el punto donde el maestro usa el máximo número de esclavos posible asignando prioridad a aquellos más rápidos. Se presentan los resultados de sintonización del tamaño de grano y número de esclavos en ejecuciones Maestro-Esclavo en entornos Grid donde se logra bajar el tiempo total de ejecución de la aplicación y aumentando la eficiencia de uso de los recursos. Se presentan las implementaciones de las aplicaciones multiplicación de matrices, N-Body y cargas sintéticas las cuales tienen diferentes grados en la relación entre cómputo y comunicación en escenarios de cambio del tamaño de grano. / When moving to Grid Computing, parallel applications face several performance problems. The system characteristics are different in each execution and sometimes within the same execution. Remote resources share network links and in some cases, the processes share machines using per-core allocation. In such scenarios we propose to use automatic performance tuning techniques to help an application adapt itself thus a system changes in order to overcome performance bottlenecks. This thesis analyzes such problems of parallel application execution in Computational Grids, available tools for performance analysis and models to suit automatic dynamic tuning in such environments. From such an analysis, we propose system architecture for automatic dynamic tuning of parallel applications on computational Grids named GMATE. Its architecture includes several contributions. In cases where a Grid meta-scheduler decides application mapping, we propose two process tracking approaches that enable GMATE to locate where a Grid middleware maps application processes. One approach consists of the integration of GMATE components as Grid middleware. The other involves the need to embed a GMATE component inside application binaries. The first requires site administration privileges while the other increases the application binary which slows down application startup. To obey organizational policies, all communications use the same application security certificates for authentication. The same communications are performed using Grid middleware API. That approach enables the monitoring and tuning process to adapt dynamically to organizational firewall restrictions and network usage policies. To lower the communication needs of GMATE, we encapsulate part of the logic required to collect measurements and change application parameters in components that run inside the processing space. For measurements collection, we create sensor components that reduce the communication needs by event processing inside the process space. Different from traditional instrumentation, sensors can postpone the event transmission and perform basic operations such as summarizations, timers, averages or threshold based event generation. That reduces the communication requirements in cases where network bandwidth is expensive. We also encapsulate the modifications used to tune the application in components called actuators. Actuators may be installed at some point in the program flow execution and provide synchronization and low overhead control of application variables and function executions. As sensors and actuators can communicate with each other, we can perform simple tuning within process executions without the need for communication. As the dynamic tuning is performance model-centric, we need a performance model that can be used on heterogeneous processors and network such Grid Systems. We propose a heuristic performance model to find the maximum number of workers and best grain size of a Master-Worker execution in such systems. We assume that some classes of application may be built capable of changing grain size at runtime and that change action can modify an application's compute-communication ratio. When users request a set of resources for a parallel execution, they may receive a multi-cluster configuration. The heuristic model allows for shrinking the set of resources without decreasing the application execution time. The idea is to reach the maximum number of workers the master can use, giving high priority to the faster ones. We presented the results of the dynamic tuning of grain size and the number of workers in Master-Worker applications on Grid systems, lowering the total application execution time while raising system efficiency. We used the implementation of Matrix-Multiplication, N-Body and synthetic workloads to try out different compute-communication ratio changes in different grain size selections.

O advento das unidades de processamento gráfico (GPUs) programáveis forneceram um novo modelo computacional que pode ser utilizado em diversas aplicações. Baseadas em arquitetura de fluxo paralelo, a atual geração de GPUs oferece processadores de vértices e de fragmentos programáveis que podem aumentar drasticamente a performance comparada com soluções implementadas exclusivamente em CPUs. Entretanto obter performance ótima no modelo computacional da GPU, que é complexo e altamente paralelo, com ferramentas de depuração limitadas é uma tarefa difícil e importante. Neste trabalho nós descrevemos uma abordagem simples para avaliar diversas soluções baseadas em GPU para uma dada solução. Ela consiste de um modelo de estimativa de performance que procura reproduzir, dentro de faixas toleráveis de erro, a medida de performance para a unidade de processamento de fragmentos. Nós avaliamos a nossa proposta utilizando as últimas gerações de placas gráficas da NVidia e da ATI usando um conjunto de medidas sintéticas bem como um estudo de caso de uma aplicação em tempo-real. / The advent of Graphics Processing Units (GPUs) with programmable shaders brought a new computational model that can be used in several applications. Based on a parallel streaming architecture, current GPU generations offer a vertex and fragment shader that can drastically improve performance if compared to CPU-only solutions. However, obtaining optimal performance in the highly parallel and complex GPU model with limited debugging tools is a challenging and important task. In this work we describe a simple approach to evaluate several GPU alternatives to a given solution. It consists of a performance estimation model that aims to reproduce within acceptable errors the measured performance of the fragment shader. We evaluate our proposal using last generation cards from NVIDIA and ATI using synthetic benchmarks as well as a real-time graphics application case-study.

O advento das unidades de processamento gráfico (GPUs) programáveis forneceram um novo modelo computacional que pode ser utilizado em diversas aplicações. Baseadas em arquitetura de fluxo paralelo, a atual geração de GPUs oferece processadores de vértices e de fragmentos programáveis que podem aumentar drasticamente a performance comparada com soluções implementadas exclusivamente em CPUs. Entretanto obter performance ótima no modelo computacional da GPU, que é complexo e altamente paralelo, com ferramentas de depuração limitadas é uma tarefa difícil e importante. Neste trabalho nós descrevemos uma abordagem simples para avaliar diversas soluções baseadas em GPU para uma dada solução. Ela consiste de um modelo de estimativa de performance que procura reproduzir, dentro de faixas toleráveis de erro, a medida de performance para a unidade de processamento de fragmentos. Nós avaliamos a nossa proposta utilizando as últimas gerações de placas gráficas da NVidia e da ATI usando um conjunto de medidas sintéticas bem como um estudo de caso de uma aplicação em tempo-real. / The advent of Graphics Processing Units (GPUs) with programmable shaders brought a new computational model that can be used in several applications. Based on a parallel streaming architecture, current GPU generations offer a vertex and fragment shader that can drastically improve performance if compared to CPU-only solutions. However, obtaining optimal performance in the highly parallel and complex GPU model with limited debugging tools is a challenging and important task. In this work we describe a simple approach to evaluate several GPU alternatives to a given solution. It consists of a performance estimation model that aims to reproduce within acceptable errors the measured performance of the fragment shader. We evaluate our proposal using last generation cards from NVIDIA and ATI using synthetic benchmarks as well as a real-time graphics application case-study.

O advento das unidades de processamento gráfico (GPUs) programáveis forneceram um novo modelo computacional que pode ser utilizado em diversas aplicações. Baseadas em arquitetura de fluxo paralelo, a atual geração de GPUs oferece processadores de vértices e de fragmentos programáveis que podem aumentar drasticamente a performance comparada com soluções implementadas exclusivamente em CPUs. Entretanto obter performance ótima no modelo computacional da GPU, que é complexo e altamente paralelo, com ferramentas de depuração limitadas é uma tarefa difícil e importante. Neste trabalho nós descrevemos uma abordagem simples para avaliar diversas soluções baseadas em GPU para uma dada solução. Ela consiste de um modelo de estimativa de performance que procura reproduzir, dentro de faixas toleráveis de erro, a medida de performance para a unidade de processamento de fragmentos. Nós avaliamos a nossa proposta utilizando as últimas gerações de placas gráficas da NVidia e da ATI usando um conjunto de medidas sintéticas bem como um estudo de caso de uma aplicação em tempo-real. / The advent of Graphics Processing Units (GPUs) with programmable shaders brought a new computational model that can be used in several applications. Based on a parallel streaming architecture, current GPU generations offer a vertex and fragment shader that can drastically improve performance if compared to CPU-only solutions. However, obtaining optimal performance in the highly parallel and complex GPU model with limited debugging tools is a challenging and important task. In this work we describe a simple approach to evaluate several GPU alternatives to a given solution. It consists of a performance estimation model that aims to reproduce within acceptable errors the measured performance of the fragment shader. We evaluate our proposal using last generation cards from NVIDIA and ATI using synthetic benchmarks as well as a real-time graphics application case-study.

The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance of modern embedded processors, they are outpaced by computational demands of the growing number of modern applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and estimate the integration overhead and consequently the hardware acceleration benefit before committing to implementation. In this work, we present FPGA-Roofline, a visual model that offers insights to designers and developers to have realistic expectations of their system and that enables them to do their design and analysis in a faster and more efficient fashion. FPGA-Roofline allows simultaneous analysis of communication and computation resources in FPGA-based hardware accelerators. To demonstrate the effectiveness of our model, we have implemented hardware accelerators in FPGA and used our model to analyze and optimize the overall system performance. We show how the same methodology can be applied to the design process of any FPGA-based hardware accelerator to increase productivity and give insights to improve performance and resource utilization by finding the optimal operating point of the system. / Master of Science

This dissertation proves the feasibility of accurate runtime prediction of processor performance under frequency scaling. The performance predictors developed in this dissertation allow processors capable of dynamic voltage and frequency scaling (DVFS) to improve their performance or energy efficiency by dynamically adapting chip or core voltages and frequencies to workload characteristics. The dissertation considers three processor configurations: the uniprocessor capable of chip-level DVFS, the private cache chip multiprocessor capable of per-core DVFS, and the shared cache chip multiprocessor capable of per-core DVFS. Depending on processor configuration, the presented performance predictors help the processor realize 72–85% of average oracle performance or energy efficiency gains. / text

The rate of data growth in many domains is straining our ability to manage and analyze it. Consequently, we see the emergence of computing systems that attempt to efficiently process data-intensive applications or I/O bound applications with large data. Cloud computing offers “infinite” resources on demand, and on a pay-as-you-go basis. As a result, it has gained interest for large-scale data processing. Given this supposedly infinite resource set, we need a provisioning process to determine appropriate resources for data processing or workload execution. We observe that the prevalent data processing architectures do not usually employ provisioning techniques available in a public cloud, and existing provisioning techniques have largely ignored data-intensive applications in public clouds. In this thesis, we take a step towards bridging the gap between existing data processing approaches and the provisioning techniques available in a public cloud, such that the monetary cost of executing data-intensive workloads is minimized. We formulate the problem of provisioning and include constructs to exploit a cloud’s elasticity to include any number of resources to host a multi-tenant database system prior to execution. The provisioning is modeled as a search problem, and we use standard search heuristics to solve it. We propose a novel framework for resource provisioning in a cloud environment. Our framework allows pluggable cost and performance models. We instantiate the framework by developing various search algorithms, cost and performance models to support the search for an effective resource configuration. We consider data-intensive workloads that consist of transactional, analytical or mixed workloads for evaluation, and access multiple database tenants. The workloads are based on standard TPC benchmarks. In addition, the user preferences on response time or throughput are expressed as constraints. Our propositions and their results are validated in a real public cloud, namely the Amazon cloud. The evaluation supports our claim that the framework is an effective tool for provisioning database workloads in a public cloud with minimal dollar cost. / Thesis (Ph.D, Computing) -- Queen's University, 2013-11-30 19:30:39.427

Master of Science / Department of Civil Engineering / Mustaque Hossain / A recent study at Kansas State University has shown that asphalt producers in Kansas are producing hot-mix asphalt (HMA) mixtures with lower asphalt contents than those in the job-mix formula. These drier mixtures are thought to be susceptible to moisture. This project evaluated the effect of asphalt content on rutting and moisture resistance of HMA. Two different mixtures and four varying asphalt contents, optimum and lower, were selected. Another large-size mixture with four varying asphalt contents was also studied. The Hamburg Wheel Tracking Device (HWTD)test (TEX-242-F) and the Kansas Standard Test-56 (KT-56), or modified Lottman test, were used to predict moisture damage and rutting potential of these mixes. All specimens tested were prepared with the Superpave gyratory compacter. Results of this study showed the drier mixtures performed better in rutting and were less susceptible to moisture.Asphalt content significantly affects the number of wheel passes in the HWTD test. The study also revealed a weak correlation between asphalt film thickness and performance test results. Thus, the effect of varying asphalt content is nonconclusive from a durability point of view. However, performance simulations using a theoretical model show that very dry mixes in asphalt pavements are likely to have shorter performance lives.