Typescript (photocopy). / Digitized by Kansas Correctional Industries / Department: Electrical and Computer Engineering.

Thesis. 1976. Ph.D.--Massachusetts Institute of Technology. Dept. of Aeronautics and Astronautics. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND AERONAUTICS. / Vita. / Bibliography : leaves 226-229. / Ph.D.

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam.

This thesis presents the design of a 2.4 GHz sub-integer-N PLL for IEEE 802.llb/g WLAN applications. The proposed PLL not only acquires the advantages of the integer-N PLL, such as simple structure and good spurious performance, but also offers some benefits (for example, faster settling time and better phase noise performance) as in the fractional-N PLL design. In this design, a novel quadrature-input programmable fractional frequency divider provides fractional division ratio in steps of 0.5 by the phase-switching technique. Its key building block is a dual divide-by-4 injection-locked frequency divider (ILFD), which is realized by coupling two conventional divide-by-4 ILFDs. Two different coupling schemes are introduced, namely the cross-coupling type and coherent-coupling type. In both schemes, symmetric configuration is maintained and hence does not degrade the PLL output phase quadrature accuracy. Furthermore, the generated phase pattern for phase switching is uniquely defined, which simplifies the phase-switching circuitry and suppresses the possibility of incorrect frequency division due to glitches. / To demonstrate the feasibility of the two proposed coupling methodologies, two subinteger-N PLLs with different fractional frequency dividers have been fabricated in a 0.35 11m standard CMOS process. In design 1, the dual divide-by-4 ILFD in the fractional frequency divider is implemented with the cross-coupling scheme while the coherent-coupling scheme is used in design 2. The measured spurious tones of both designs are under -64 dBc and their measured phase noise at 1 MHz frequency offset is less than -115 dBc/Hz. The two proposed frequency synthesizers settle at approximately 32 us and their phase mismatches of the quadrature outputs are better than 38 dB (characterized by image rejection ratio). Moreover, both designs individually occupy a chip area as small as 0.70 mm2. At a supply of 1.5 V, the total power consumption for each design is below 24.1 mW. / Wireless local area networks (WLANs) are being extensively deployed since their introduction in the late 1990s. Low cost, high performance frequency synthesizers are indispensable in WLAN telecommunication systems. Meanwhile, integer-N phase-locked loop (PLL) architecture is commonly chosen due to its low circuit complexity and clean output spectrum with few spurs. However, designers have to face the tradeoffs between frequency resolution, phase noise performance and switching time. To solve the above dilemma, fractional-N PLL architecture is proposed, but fractional spurs emerge in the output spectrum, degrading the spectrum purity. Sub-integer-N PLL is thus a compromise between the integer-N and fractional-N PLL. Its structure is same as that of the integer-N while fractional division is achieved by a fractional frequency divider that is not relied on time-varying modulus control as in the fractional-N PLL. / Chang, Ka Fai. / Adviser: Kwok-Keung Cheng. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 176-188). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

<p>POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes.</p><p>This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.</p>

Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations. / Graduation date: 2013

As Moore���s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area. The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a ��-�� DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to-peak jitter and -50dbC/Hz reference spurs. / Graduation date: 2012

Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area occupied by the large loop filter capacitor and resistor in a low bandwidth PLL design makes the realization of traditional charge-pump PLL architecture impractical on a single die, mandating external components on the board. In order to maintain low loop bandwidth the designer is often forced to choose very low values of charge pump current which can lead to reliability issues. In this work, a semi-digital architecture for very low bandwidth monolithic PLLs is proposed. This architecture eliminates large components in traditional charge-pump PLL, thus allowing the realization of on-chip low bandwidth PLLs. A 2x2mm PLL is realized in 180nm CMOS with 75mHz bandwidth consuming 400μW power from 1.8V supply. The prototype PLL locks to an input clock of 1Hz and generates 20kHz output clock with a measured peak-to-peak jitter of 100ns. / Graduation date: 2013

The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.

POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes. This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.