Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references. Also available on the World Wide Web.

Thesis (M.S.)--University of Michigan, 1974.

Thesis (M.S.)--West Virginia University, 2004. / Title from document title page. Document formatted into pages; contains vii, 49 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 44-45).

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--University of Southern California, 1999. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Thesis (M.S.)--University of Michigan, 1983.

Thesis (M.S.)--University of Michigan, 1974.

Thesis (Ph. D.)--University of Southern California, 1999. / Includes bibliographical references.

Thesis (M.A.)--West Virginia University, 2005. / Title from document title page. Document formatted into pages; contains ix, 191 p. : ill. (some col.), col. map. Includes abstract. Includes bibliographical references (p. 111-116).

Ce travail porte sur la caractérisation et la modélisation des fluctuations aléatoires des paramètres électriques des transistors MOS avancées. La structure de test utilisée est validée expérimentalement au moyen de la méthode de mesure de Kelvin. Pour comprendre le comportement des fluctuations, un modèle est d’abord proposé pour le régime linéaire. Il permet de modéliser les fluctuations de la tension de seuil des transistors avec implants de poche pour toutes les longueurs de transistor et aussi pour toute la gamme de tension de grille. Ensuite, l’appariement du courant de drain est caractérisé et modélisé en fonction de la tension de drain. Pour modéliser les caractéristiques réelles de transistors sans implants de poche, il est nécessaire de considérer la corrélation des fluctuations de la tension de seuil et celles de la mobilité. De plus, des caractérisations sur des transistors avec implants de poche montrent un nouveau comportement de l’appariement du courant de drain. Des caractérisations ont aussi été menées pour analyser l’impact des fluctuations de la rugosité de grille. / This research characterizes and models the mismatch of electrical parameters in advanced MOS transistors. All characterizations are made through a test structure, which is experimentally validated using a structure based on Kelvin method. A model, valid in the linear region, is proposed. It is used for modeling the threshold voltage fluctuations of the transistors with pocket-implants, for any transistor length and gate voltage. It gives a deep understanding of the mismatch, especially for devices with non-uniform channel. Another study analyzes the mismatch of the drain current by characterizing and modeling in terms of the drain voltage. A second model is then proposed for transistors without pocket-implants. In order to apply this model, the correlation of threshold voltage fluctuations and mobility fluctuations must be considered. Characterizations are also performed on transistors with pocket-implants, showing a new drain current mismatch behavior for long transistors. Finally, characterizations are made to analyze the impact of gate roughness fluctuations on mismatch.