L’évolution des services en ligne et l’avènement du big data ont favorisé l’introduction de l’internet dans tous les aspects de notre vie : la communication et l’échange des informations (exemple, Gmail et Facebook), la recherche sur le web (exemple, Google), l’achat sur internet (exemple, Amazon) et le streaming vidéo (exemple, YouTube). Tous ces services sont hébergés sur des sites physiques appelés centres de données ou data centers qui sont responsables de stocker, gérer et fournir un accès rapide à toutes les données. Tous les équipements constituants le système d’information d’une entreprise (ordinateurs centraux, serveurs, baies de stockage, équipements réseaux et de télécommunications, etc) peuvent être regroupés dans ces centres de données. Cette évolution informatique et technologique a entrainé une croissance exponentielle des centres de données. Cela pose des problèmes de coût d’installation des équipements, d’énergie, d’émission de chaleur et de performance des services offerts aux clients. Ainsi, l’évolutivité, la performance, le coût, la fiabilité, la consommation d’énergie et la maintenance sont devenus des défis importants pour ces centres de données. Motivée par ces défis, la communauté de recherche a commencé à explorer de nouveaux mécanismes et algorithmes de routage et des nouvelles architectures pour améliorer la qualité de service du centre de données. Dans ce projet de thèse, nous avons développé de nouveaux algorithmes et architectures qui combinent les avantages des solutions proposées, tout en évitant leurs limitations. Les points abordés durant ce projet sont: 1) Proposer de nouvelles topologies, étudier leurs propriétés, leurs performances, ainsi que leurs coûts de construction. 2) Conception des algorithmes de routage et des modèles pour réduire la consommation d’énergie en prenant en considération la complexité, et la tolérance aux pannes. 3) Conception des protocoles et des systèmes de gestion de file d’attente pour fournir une bonne qualité de service. 4) Évaluation des nouveaux systèmes en les comparants à d’autres architectures et modèles dans des environnements réalistes. / The increasing trend to migrate applications, computation and storage into more robust systems leads to the emergence of mega data centers hosting tens of thousands of servers. As a result, designing a data center network that interconnects this massive number of servers, and providing efficient and fault-tolerant routing service are becoming an urgent need and a challenge that will be addressed in this thesis. Since this is a hot research topic, many solutions are proposed like adapting new interconnection technologies and new algorithms for data centers. However, many of these solutions generally suffer from performance problems, or can be quite costly. In addition, devoted efforts have not focused on quality of service and power efficiency on data center networks. So, in order to provide a novel solution that challenges the drawbacks of other researches and involves their advantages, we propose to develop new data center interconnection networks that aim to build a scalable, cost-effective, high performant and QoS-capable networking infrastructure. In addition, we suggest to implement power aware algorithms to make the network energy effective. Hence, we will particularly investigate the following issues: 1) Fixing architectural and topological properties of the new proposed data centers and evaluating their performances and capacities of providing robust systems under a faulty environment. 2) Proposing routing, load-balancing, fault-tolerance and power efficient algorithms to apply on our architectures and examining their complexity and how they satisfy the system requirements. 3) Integrating quality of service. 4) Comparing our proposed data centers and algorithms to existing solutions under a realistic environment. In this thesis, we investigate a quite challenging topic where we intend, first, to study the existing models, propose improvements and suggest new methodologies and algorithms.

In the design of the state-of-the-art electronic products, power management circuits play a very important role for the enhancement of overall system efficiency. Switched mode DC-DC converter is an increasingly popular power management circuit due to its superior power conversion efficiency. This thesis introduces two efficiency optimization techniques for switched mode power electronic circuits. One is dead-time optimization. This technique can automatically adjust the dead-time on-the-fly according to the circuit operating conditions. Second, an energy conservation based high-efficiency dimmable multi-channel LED driver is discussed. An auxiliary power switched is use to allow free wheeling of the inductor current during the load disconnect period. The sequential burst mode PWM current sharing scheme with dimming capability can effectively reduce design complexity and cost. The proposed LED driver provides a practical solution for the realization of LED BLU in the flat panel TVs with local dimming capability according to the video content.

In the design of the state-of-the-art electronic products, power management circuits play a very important role for the enhancement of overall system efficiency. Switched mode DC-DC converter is an increasingly popular power management circuit due to its superior power conversion efficiency. This thesis introduces two efficiency optimization techniques for switched mode power electronic circuits. One is dead-time optimization. This technique can automatically adjust the dead-time on-the-fly according to the circuit operating conditions. Second, an energy conservation based high-efficiency dimmable multi-channel LED driver is discussed. An auxiliary power switched is use to allow free wheeling of the inductor current during the load disconnect period. The sequential burst mode PWM current sharing scheme with dimming capability can effectively reduce design complexity and cost. The proposed LED driver provides a practical solution for the realization of LED BLU in the flat panel TVs with local dimming capability according to the video content.

Today’s computer systems develop towards less energy consumption while keeping high performance. These are contradictory requirement and pose a great challenge. A good example of an application were this is used is the smartphone. The constraints are on long battery time while getting high performance required by future 2D/3D applications. A solution to this is heterogeneous systems that have components that are specialized in different tasks and can execute them fast with low energy consumption. These could be specialized i.e. encoding/decoding, encryption/decryption, image processing or communication. At the apartment of Computer Architecture and Parallel Processing Laboratory (CAPPL) at New Jersey Institute of Technology (NJIT) a vector co-processor has been developed. The Vector co-processor has the unusual feature of being able to receive instructions from multiple hosts (scalar cores). In addition to this a test system with a couple of scalar processors using the vector processor has been developed. This thesis describes this processor and its test system. It also shows the development of math applications involving matrix operations. This results in the conclusions of the vector co-processing saving substantial amount of energy while speeding up the execution of the applications. In addition to this the thesis will describe an extension of the vector co-processor design that makes it possible to monitor the throughput of instructions and data in the processor.

Along with the rapidly increasing demand for high data rate communications, orthogonal frequency division multiplexing (OFDM) has become a popular modulation in current and future communication standards. By distributing a high-speed data stream to many parallel low-rate data streams, OFDM is able to mitigate the detrimental effects of multipath fading using simple one-tap equalizers and achieve high spectral efficiency. However, the OFDM signal waveform suffers from large envelop variations, which are usually measured by the peak-to-average power ratio (PAR). In wireless transmitters, many RF components, especially the power amplifiers, are inherently nonlinear and peak power constrained. Therefore, low power efficiency and/or severe nonlinear distortions are the main shortcomings of OFDM systems. In this dissertation, we develop algorithms and analyze performance bounds for peak power constrained wireless communications. To address the balance between power efficiency and nonlinear distortions, we model the peak power constrained OFDM systems in both statistical and deterministic manners. We first propose an error vector magnitude (EVM) optimization algorithm to strictly satisfy the distortion requirements in accordance with communication standards and provide the maximum power efficiency for OFDM transmitters without receiver-side cooperations. Moreover, we develop a multi-channel partial transmit sequence (MCPTS) PAR reduction method for OFDM-based frequency-division multiple access (OFDM-FDMA) multiuser systems, which can achieve significant power efficiency improvement without using side information. Joint MCPTS and power allocation schemes are also proposed to improve the error performance of OFDM-FDMA systems. Furthermore, diversity-enabled communication systems have practical merits in combating channel fadings. Therefore, in the second part of this dissertation, peak power constrained diversity techniques are proposed. The error performance of peak power constrained single-input multiple-output (SIMO) OFDM is studied. Several low-complexity SIMO-OFDM transceiver designs are presented to collect full antenna diversity with respective performance and complexity tradeoffs. The next major piece of work in this dissertation addresses the design of peak power constrained amplify-and-forward (AF) cooperative networks, which enable the cooperative diversity with single-antenna terminals. The effects of the availability of channel state information and the peak power constraint on the diversity performance are theoretically studied. Design criteria for general diversity-enabled AF relaying strategies are established and further applied to the designs in peak power constrained networks. In the end, a general theorem that relates the diversity gain function with the probability density function of instantaneous signal-to-noise ratio is derived and used to analyze the diversity performance of relay selection schemes.

This thesis describes fundamental approaches to quantify rate versus power consumption tradeoffs for cascaded communication systems. The discussion is bolstered by a large number of in-situ channel measurements, which are used in discussions of the power consumption of future massively broadband cellular systems. Chapter one provides an introduction. Chapter two discusses power consumption trends in modern communication systems. Chapter three introduces the consumption factor framework. Chapter four discusses the channel measurement campaign. Chapter five concludes the thesis, and uses the measurement results to estimate power consumption and capacity of future cellular systems. In addition, chapter five extends the consumption factor theory and draws fundamental conclusions about the energy price per bit for a general cascaded communication system. / text

Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry. Power dissipation, increasing wire delays, and increasing design complexity have forced industry to embrace multi-core architectures or chip multiprocessors (CMPs). While CMPs mitigate wire delays and design complexity, they do not directly address single-threaded performance. Additionally, programs must be parallelized, either manually or automatically, to fully exploit the performance of CMPs. Researchers have recently proposed an architecture called Explicit Data Graph Execution (EDGE) as an alternative to conventional CMPs. EDGE architectures are designed to be technology-scalable and to provide good single-threaded performance as well as exploit other types of parallelism including data-level and thread-level parallelism. In this dissertation, we examine the energy efficiency of a specific EDGE architecture called TRIPS Instruction Set Architecture (ISA) and two microarchitectures called TRIPS and TFlex that implement the TRIPS ISA. TRIPS microarchitecture is a first-generation design that proves the feasibility of the TRIPS ISA and distributed tiled microarchitectures. The second-generation TFlex microarchitecture addresses key inefficiencies of the TRIPS microarchitecture by matching the resource needs of applications to a composable hardware substrate. First, we perform a thorough power analysis of the TRIPS microarchitecture. We describe how we develop architectural power models for TRIPS. We then improve power-modeling accuracy using hardware power measurements on the TRIPS prototype combined with detailed Register Transfer Level (RTL) power models from the TRIPS design. Using these refined architectural power models and normalized power modeling methodologies, we perform a detailed performance and power comparison of the TRIPS microarchitecture with two different processors: 1) a low-end processor designed for power efficiency (ARM/XScale) and 2) a high-end superscalar processor designed for high performance (a variant of Power4). This detailed power analysis provides key insights into the advantages and disadvantages of the TRIPS ISA and microarchitecture compared to processors on either end of the performance-power spectrum. Our results indicate that the TRIPS microarchitecture achieves 11.7 times better energy efficiency compared to ARM, and approximately 12% better energy efficiency than Power4, in terms of the Energy-Delay-Squared (ED²) metric. Second, we evaluate the energy efficiency of the TFlex microarchitecture in comparison to TRIPS, ARM, and Power4. TFlex belongs to a class of microarchitectures called Composable Lightweight Processors (CLPs). CLPs are distributed microarchitectures designed with simple cores and are highly configurable at runtime to adapt to resource needs of applications. We develop power models for the TFlex microarchitecture based on the validated TRIPS power models. Our quantitative results indicate that by better matching execution resources to the needs of applications, the composable TFlex system can operate in both regimes of low power (similar to ARM) and high performance (similar to Power4). We also show that the composability feature of TFlex achieves a signification improvement (2 times) in the ED² metric compared to TRIPS. Third, using TFlex as our experimental platform, we examine the efficacy of processor composability as a potential performance-power trade-off mechanism. Most modern processors support a form of dynamic voltage and frequency scaling (DVFS) as a performance-power trade-off mechanism. Since the rate of voltage scaling has slowed significantly in recent process technologies, processor designers are in dire need of alternatives to DVFS. In this dissertation, we explore processor composability as an architectural alternative to DVFS. Through experimental results we show that processor composability achieves almost as good performance-power trade-offs as pure frequency scaling (no changes in supply voltages), and a much better performance-power trade-off compared to voltage and frequency scaling (both supply voltage and frequency change). Next, we explore the effects of additional performance-improving techniques for the TFlex system on its energy efficiency. Researchers have proposed a variety of techniques for improving the performance of the TFlex system. These include: (1) block mapping techniques to trade off intra-block concurrency with communication across the operand network; (2) predicate prediction and (3) operand multi-cast/broadcast mechanism. We examine each of these mechanisms in terms of its effect on the energy efficiency of TFlex, and our experimental results demonstrate the effects of operand communication, and speculation on the energy efficiency of TFlex. Finally, this dissertation evaluates a set of fine-grained power management (FGPM) policies for TFlex: instruction criticality and controlled speculation. These policies rely on a temporally and spatially fine-grained dynamic voltage and frequency scaling (DVFS) mechanism for improving power efficiency. The instruction criticality policy seeks to improve power efficiency by mapping critical computation in a program to higher performance-power levels, and by mapping non-critical computation to lower performance-power levels. Controlled speculation policy, on the other hand, maps blocks that are highly likely to be on correct execution path in a program to higher performance levels, and the other blocks to lower performance levels. Our experimental results indicate that idealized instruction criticality and controlled speculation policies improve the operating range and flexibility of the TFlex system. However, when the actual overheads of fine-grained DVFS, especially energy conversion losses of voltage regulator modules (VRMs), are considered the power efficiency advantages of these idealized policies quickly diminish. Our results also indicate that the current conversion efficiencies of on-chip VRMs need to improve to as high as 95% for the realistic policies to be feasible. / text

The great innovations of the last century have ushered continuous progress in many areas of technology, especially in the form of miniaturization of electronic circuits. This progress shows a trend towards consistent decreases in power requirements due to miniaturization. According to the ITRS and industry leaders, such as Intel, the challenge of managing and providing power efficiency still persist as scaling down of devices continues. A variety of power sources can be used in order to provide power to low power applications. Few of these sources have favorable characteristics and can be designed to deliver maximum power such as the novel mini notched turbine used as a source in this work. The MiNT is a novel device that can be used as a feasible energy source when integrated into a system and evaluated for power delivery as investigated in this work. As part of this system, a maximum power point tracking system provides an applicable solution for capturing enhanced power delivery for an energy harvesting system. However, power efficiency and physical size are adversely affected by the characteristics and environment of many energy harvesting systems and must also be addressed. To address these issues, an analysis of mini notched turbine, a RF rectenna, and an enhanced maximum power point tracking system is presented and verified using simulations and measurements. Furthermore, mini notched energy harvesting system, RF rectenna energy harvesting system, and enhanced maximum power point tracking system are developed and experimental data analyzed. The enhanced maximum power point tracking system uses a resistor emulation technique and particle swarm optimization (PSO) to improve the power efficiency and reduce the physical size. This new innovative design improves the efficiency of optimized power management circuitry up to 7% compared to conventional power management circuits over a wide range of input power and range of emulated resistances, allowing more power to be harvested from small energy harvesting sources and delivering it to the load such as smart sensors. In addition, this is the first IC design to be implemented and tested for the patented mini notched turbine (MiNT) energy harvesting device. Another advantage of the enhanced power management system designed in this work is that the proposed approach can be utilized for extremely small energy sources and because of that the proposed work is valid for low emulated resistances. and systems with low load resistance Overall, through the successful completion of this work, various energy harvesting systems can have the ability to provide enhanced power management as the IC industry continues to progress toward miniaturization of devices and systems.

The purpose of this research is to design and integrate a symbiotic notched-turbine energy generator for implantation as a cross-coupled system capable of continuously and perpetually powering an electronic implantable medical device (IMD), which is a device designed to operate inside the body of a higher mammal to enhance, correct or provide the body with a function that has deviated from the norm or has stopped altogether. The list of IMDs available for implantation keeps growing every year, one of the newest being the VBLOC, produced by EnteroMedics®, and approved by the Food and Drug Administration (FDA) on January 15th, 2015[1], [2] to treat obesity in the United States, in lieu of the more dangerous and costly bariatric surgery widely used to treat the same condition. Some of the more traditional IMDs, such as the cardiac defibrillator, pacemaker, and insulin pumps require the use of a battery system for their operation. The powering of IMDs is a topic of growing importance and as such, the energy released by the hydrodynamic action of the cardiovascular system of a higher mammal is presented in this work as a source of energy that can be converted into electricity by use of a microturbine, loaded with magnetic rings that induce a time-varying magnetic field onto a set of insulated coils through the process of electromagnetic induction (EMI) in accordance with Faraday’s Law. This work goes beyond mere power production and focuses on the process required to integrate this power source with an IMD when it is coupled to the cardiovascular system for drawing hydro-mechanical power for conversion to electricity and to the IMD of choice to xii deliver the conditioned power, thus replicating a symbiotic process. The harvested energy in the form of a time-varying tri-phase sine wave is therefore rectified, conditioned and made available for use to the IMD. The proposed 3-phase generator has a volume of 1.02 cm3 and has the potential to be implemented as a dual or quad system that doubles or quadruples the single generator power capabilities accordingly. The rectifying and conditioning circuits may be housed in a hermetically sealed container, covered with a biocompatible material such as, ultra-high molecular weight polyethylene (UHMWPE), polymethylmethacrylate (PMMA) or titanium, which can afford the best implantation properties such as non-absorbability, durability, hardness, and biocompatibility [4]. Additionally, the prevention of blood clotting is of paramount importance in any IMD, which can be helped, for example by treating its surface with Tethered-Liquid Perfluorocarbons (TLP) to prevent biofilm formation of the blood that typically leads to infections and clotting[5].

Pour répondre aux besoins de plus en plus hétérogènes des applications (puissance et efficacité énergétique), nous nous intéressons dans cette thèse aux architectures émergentes de type multi-cœur asymétrique en fonctionnalités (FAMP). Ces architectures sont caractérisées par une mise en œuvre non-uniforme des extensions matérielles dans les cœurs (ex. unitée de calculs à virgule flottante (FPU)). Les avantages en surface sont apparents, mais qu'en est-il de l'impact au niveau logiciel, énergétique et performance?Pour répondre à ces questions, la thèse explore la nature de l'utilisation des extensions dans des applications de l'état de l'art et compare différentes méthodes existantes. Pour optimiser le placement de tâches et ainsi augmenter l'efficacité, la thèse propose une solution dynamique au niveau ordonnanceur, appelée ordonnanceur relaxé.Les extensions matérielles sont intéressantes car elles permettent des accélérations difficilement atteignables par la parallélisation sur un multi-cœur. Néanmoins, leurs utilisations par les applications sont faibles et leur coût en termes de surface et consommation énergétique sont importants.En se basant sur ces observations, les points suivants ont été développés:Nous présentons une étude approfondie sur l'utilisation de l'extension vectorielle et FPU dans des applications de l'état de l'artNous comparons plusieurs solutions de gestion des extensions à différent niveaux de granularité temporelle d'action pour comprendre les limites de ces solutions et ainsi définir à quel niveau il faut agir. Peu d'études traitent la question de la granularité d'action pour gérer les extensions.Nous proposons une solution pour estimer en ligne la dégradation de performance à exécuter une tâche sur un cœur sans extension. Afin de permettre la mise à l'échelle des multi-cœurs, le système d'exploitation doit avoir de la flexibilité dans le placement de tâches. Placer une tâche sur un cœur sans extension peut avoir d'importantes conséquences en énergie et en performance. Or à ce jour, il n'existe pas de solution pour estimer cette potentielle dégradation.Nous proposons un ordonnanceur relaxé, basé notre modèle d'estimation de dégradation, qui place les tâches sur un ensemble de cœurs hétérogènes de manière efficace. Nous étudions la flexibilité gagnée ainsi que les conséquences aux niveaux performances et énergie.Les solutions existantes proposent des méthodes pour placer les tâches sur un ensemble de cœurs hétérogènes, or, celles-ci n'étudient pas le compromis entre qualité de service et gain en consommation pour les architectures FAMP.Nos expériences sur simulateur ont montré que l'ordonnanceur peut atteindre une flexibilité de placement significative avec une dégradation en performance de moins de 2%. Comparé à un multi-cœur symétrique, notre solution permet un gain énergétique moyen au niveau cœur de 11 %. Ces résultats sont très encourageant et contribuent au développement d'une plateforme complète FAMP. Cette thèse a fait l'objet d'un dépôt de brevet, de trois communications scientifiques internationales (plus une en soumission), et a contribué à deux projets européens. / To meet the increasingly heterogeneous needs of applications (in terms of power and efficiency), this thesis focus on the emerging functionally asymmetric multi-core processor (FAMP) architectures. These architectures are characterized by non-uniform implementation of hardware extensions in the cores (ex. Floating Point Unit (FPU)). The area savings are apparent, but what about the impact in software, energy and performance?To answer these questions, the thesis investigates the nature of the use of extensions in state-of-the-art's applications and compares various existing methods. To optimize the tasks mapping and increase efficiency, the thesis proposes a dynamic solution at scheduler level, called relaxed scheduler.Hardware extensions are valuable because they speed up part of code where the parallelization on multi-core isn't efficient. However, the hardware extensions are under-exploited by applications and their cost in terms of area and power consumption are important.Based on these observations, the following contributions have been proposed:We present a detailed study on the use of vector and FPU extensions in state-of-the-art's applicationsWe compare multiple extension management solutions at different levels of temporal granularity of action, to understand the limitations of these solutions and thus define at which level we must act. Few studies address the issue of the granularity of action to manage extensions.We offer a solution for estimating online performance degradation to run a task on a core without a given extension. To allow the scalability of multi-core, the operating system must have flexibility in the placement of tasks. Placing a task on a core with no extension can have important consequences for energy and performance. But to date, there is no way to estimate this potential degradation.We offer a relaxed scheduler, based on our degradation estimation model, which maps the tasks on a set of heterogeneous cores effectively. We study the flexibility gained and the implications for performance and energy levels. Existing solutions propose methods to map tasks on a heterogeneous set of cores, but they do not study the tradeoff between quality of service and consumption gain for FAMP architectures.Our experiments with simulators have shown that the scheduler can achieve a significantly higher mapping flexibility with a performance degradation of less than 2 %. Compared to a symmetrical multi-core, our solution enables an average energy gain at core level of 11 %. These results are very encouraging and contribute to the development of a comprehensive FAMP platform . This thesis has been the subject of a patent application, three international scientific communications (plus one submission), and contributes to two active european projects.