Made available in DSpace on 2015-05-08T14:59:42Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 5430085 bytes, checksum: 2ce42198a2dd4ca16f3d08b584e0513c (MD5) Previous issue date: 2012-06-20 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / The objective of this research was to develop a nonlinear controller, using the technique of fuzzy intelligent control, apply to networks pressurized water distribution sectored, automated and distributed pumping system in order to minimize energy consumption. The methodology used was based on the performance of several tests using an instrumented experimental network, where the control system can be tested and evaluated. The experimental system has pressure transducers and flow, variable speed driven, proportional control valves and water distribution lines, with different topologies that allow you to simulate dynamically different situations operational supply network, depending on the variation of demand water over time. The supervisory system built acquires the necessary data, provided by the network monitoring tools. The controller module of the supervisory system processes data in real time, tuning the instruments to carefully control the experimental network. We performed numerous tests with different operating conditions in order to extract rules and various combinations of control, to optimize the balance of pressures on the network and reduce energy consumption. The results obtained proved that it is more economical to operate the network with the two sets of pumping, for all ranges of consumption studied. Besides the economic aspect, which indicated an energy saving of around 12.17%, the controller gave better performance to achieve and balance the pressures of the network with the pumping action of two acting simultaneously. / O objetivo nesta pesquisa foi desenvolver um controlador não-linear, utilizando a técnica de controle inteligente fuzzy, aplicável a redes pressurizadas de distribuição de água setorizadas, automatizadas e com sistema de bombeamento distribuído, visando minimizar o consumo de energia elétrica. A metodologia empregada foi baseada na realização de diversos ensaios utilizando uma rede experimental instrumentalizada, onde o sistema de controle pode ser testado e avaliado. O sistema experimental possui transdutores de pressão e de vazão, conversores de frequência, válvulas com controle proporcional e ramais de distribuição de água, com topologias diferentes que permitem simular, dinamicamente, diversas situações operacionais da rede de abastecimento, em função da variação da demanda de água ao longo do tempo. O sistema supervisório construído adquire os dados necessários, fornecidos pelos instrumentos de monitoramento da rede. O módulo controlador do sistema supervisório processa os dados, em tempo real, sintonizando de forma criteriosa os instrumentos de controle da rede experimental. Foram realizados inúmeros ensaios com diferentes condições operacionais, visando extrair regras e combinações diversas de controle, para otimizar o equilíbrio das pressões na rede e reduzir o consumo energético. Os resultados obtidos comprovaram que é mais econômico operar a rede com os dois conjuntos de bombeamento, para todas as faixas de consumo estudadas. Além do aspecto econômico, que indicou uma economia de energia da ordem de 12,17%, o controlador proporcionou um melhor desempenho para atingir e equilibrar as pressões da rede com a ação dos dois bombeamentos atuando simultaneamente.

Cette thèse porte sur les architectures d’émission pour des terminaux mobiles multi-radio fonctionnant dans la bande de fréquences, 800 MHz - 6 GHz. Avec l’évolution constante des systèmes de communication, les terminaux doivent fonctionner dans plusieurs bandes de fréquences et modes, correspondant à une grande diversité de normes. Le concept d’une architecture multi-radio unique est une évolution de celui de l’émetteur-récepteur multistandard, caractérisé par une mise en parallèle des circuits pour chaque standard. Il permet alors d’optimiser coût et consommation. L’objet de l’étude est de concevoir des architectures d’émission flexibles, à la fois en fréquence et en format de modulation, capables de générer les formes d’ondes de tous les standards en respectant pour chacun le niveau de puissance en sortie et assurant un bon rendement. Ce type d’architectures pourrait, dans l’avenir, être utilisé pour des applications de radio cognitive. L’amplificateur de puissance est l’élément critique dans les émetteurs. Le principe de fonctionnement des amplificateurs impose un compromis entre la linéarité et le rendement en puissance. L’utilisation des amplificateurs en classes commutées permet d’améliorer les performances en rendement mais nécessite de revoir complètement les architectures classiques d’émission. Dans ce contexte, plusieurs architectures qui transforment les signaux avant l’amplificateur et qui peuvent être utilisées pour la multi-radio ont été considérées. Trois, en particulier, ont été analysées et comparées ; à savoir : l’architecture polaire avec codeur d’enveloppe sigma-delta, l’architecture polaire avec codeur d’enveloppe par largeur d’impulsion et l’architecture cartésienne sigma-delta. La validation a été faite sur les signaux les plus critiques en matière de dynamique de puissance et de bande passante, que sont les signaux LTE et WiMAX mobile. En sortie de l’amplificateur, le filtrage d’émission joue un rôle décisif et plusieurs technologies de filtrage sont envisageables. Dans ce cadre, on s’est plus particulièrement intéressé à la technologie BAW (Bulk Acoustic Wave) et un banc de filtres multi-radio a été synthétisé. Cette thèse a donc permis de chiffrer les performances clés d’un émetteur multi-radio à haut rendement en analysant du traitement en bande de base jusqu’au filtrage d’antenne / This research deals with wireless multi-radio transmitter architectures operating in the frequency band of 800 MHz – 6GHz. As a consequence of the constant evolution in the communication systems, the mobile transmitters must be able to operate at different frequency bands and modes according to existing standards specifications. The concept of a unique multi-radio architecture is an evolution of the multi-standard transceiver characterized by a parallelization of circuits for each standard. Multi-radio concept optimizes surface and power consumption. This study concentrates on flexible multi-radio architectures. This kind of architectures could be used in the future for cognitive radio applications. The power amplifier (PA) is the key element in transmitter architectures. Its operating principle establishes a trade-off between power efficiency and linearity. The utilization of a switched mode amplifier allows improving efficiency performances but implies a review of the classical transmitter architectures. Within this context, some architectures transforming the input signal of the PA and that are candidates for multi-radio applications are considered. In particular, three architectures have been analyzed and compared: the polar architecture with sigma-delta envelope modulator, the polar architecture with pulse width modulator and the cartesian sigma delta architecture. Validation is accomplished with the most critical signals in terms of power dynamics and frequency bandwidth; these are the LTE and mobile WiMAX. At the amplifier output, the band-pass filter plays a key role and many filtering technologies could be envisaged. In particular, we are interested in the BAW technology (Bulk Acoustic Wave) and a filter bank has been synthesized. This research has quantified the key performances of a high efficiency multi-radio transmitter by analyzing the system from baseband signal treatment to RF filtering before the antenna

The semiconductor industry has been driven by Moore's law for almost half a century. Miniaturization of device size has allowed more transistors to be packed into a smaller area while the improved transistor performance has resulted in a significant increase in frequency. Increased density of devices and rising frequency led, unfortunately, to a power density problem which became an obstacle to further integration. The processor industry responded to this problem by lowering processor frequency and integrating multiple processor cores on a die, choosing to focus on Thread Level Parallelism (TLP) for performance instead of traditional Instruction Level Parallelism (ILP). While continued scaling of devices have provided unprecedented integration, it has also unfortunately led to a few serious problems: The first problem is that of increasing rates of system failures due to soft errors and aging defects. Soft errors are caused by ionizing radiations that originate from radioactive contaminants or secondary release of charged particles from cosmic neutrons. Ionizing radiations may charge/discharge a storage node causing bit flips which may result in a system failure. In this dissertation, we propose solutions for online detection of such errors in microprocessors. A small and functionally limited core called the Sentry Core (SC) is added to the multicore. It monitors operation of the functional cores in the multicore and whenever deemed necessary, it opportunistically initiates Dual Modular redundancy (DMR) to test the operation of the cores in the multicore. This scheme thus allows detection of potential core failure and comes at a small hardware overhead. In addition to detection of soft errors, this solution is also capable of detecting errors introduced by device aging that results in failure of operation. The solution is further extended to verify cache coherence transactions. A second problem we address in this dissertation relate to power concerns. While the multicore solution addresses the power density problem, overall power dissipation is still limited by packaging and cooling technologies. This limits the number of cores that can be integrated for a given package specification. One way to improve performance within this constraint is to reduce power dissipation of individual cores without sacrificing system performance. There have been prior solutions to achieve this objective that involve Dynamic Voltage and Frequency Scaling (DVFS) and the use of sleep states. DVFS and sleep states take advantage of coarse grain variation in demand for computation. In this dissertation, we propose techniques to maximize performance-per-power of multicores at a fine grained time scale. We propose multiple alternative architectures to attain this goal. One of such architectures we explore is Asymmetric Multicore Processors (AMPs). AMPs have been shown to outperform the symmetric ones in terms of performance and Performance-per-Watt for a fixed resource and power budget. However, effectiveness of these architectures depends on accurate thread-to-core scheduling. To address this problem, we propose online thread scheduling solutions responding to changing computational requirements of the threads. Another solution we consider is for Symmetric Multicore processors (SMPs). Here we target sharing of the large and underutilized resources between pairs of cores. While such architectures have been explored in the past, the evaluations were incomplete. Due to sharing, sometimes the shared resource is a bottleneck resulting in significant performance loss. To mitigate such loss, we propose the Dynamic Voltage and Frequency Boosting (DVFB) of the shared resources. This solution is found to significantly mitigate performance loss in times of contention. We also explore in this dissertation, performance-per-Watt improvement of individual cores in a multicore. This is based on dynamic reconfiguration of individual cores to run them alternately in out-of-order (OOO) and in-order (InO) modes adapting dynamically to workload characteristics. This solution is found to significantly improve power efficiency without compromising overall performance. Thus, in this dissertation we propose solutions for several important problems to facilitate continued scaling of processors. Specifically, we address challenges in the area of reliability of computation and propose low power design solutions to address power constraints.

This research presents design techniques for a linear power amplifier with high efficiency in wireless handsets. The power amplifier operates with high efficiency at the saturated output power, maintains high linearity with enhanced efficiency at back-off power levels, and covers a broadband frequency response. The amplifier is thus able to operate in multiple modes (2G/2.5G/3G/4G). The design techniques provide contributions to current research in handset power amplifiers, especially to the converged power amplifier architecture, to reduce the number of power amplifiers within the handset while covering all standards and frequency bands around the globe. Three main areas of interest in power amplifier design are investigated: high power efficiency; high linearity; and broadband frequency response. Multiple techniques for improving the efficiency are investigated with the focus on maintaining linear operation. The research applies a new technique to the handset industry, class-J, to improve the power efficiency while avoiding the practical issues that hinder the typical techniques (class-AB and class-F). Class-J has been implemented using GaN FET in high power applications. To our knowledge, this work provides the first implementation of class-J using GaAs HBT in a handset power amplifier. The research investigates the linearity, and the nature and causes of nonlinearities. Multiple concepts for improving the linearity are presented, such as avoiding odd-degree harmonics, and linearizing the relationship between the output current and the input voltage of the amplifier at the fundamental frequency. The concept of bias depression in HBT transistors is introduced with a bias circuit that reduces the bias-offset effect to improve linearity at high output power. A design methodology is presented for broadband matching networks, including the component loss. The methodology offers a quick and accurate estimation of component values, giving more degrees of freedom to meet the design specifications. It enables a trade-off among high out-of-band attenuation, number/size of components, and power loss within the network. Although the main focus is handset power amplifiers, most of the developed techniques can be applied to a wide range of power amplifiers. / Ph. D.

Ces travaux présentent l'étude de transformateurs par voie acoustique, basés sur la technologie CMUT (Capacitive Micromachined Ultrasonic Transducer ), visant à développer des composants monolithiques assurant l'isolation électrique au sein de la commande des interrupteurs à semi-conducteurs. S'agissant de microsystèmes électromécaniques, les CMUTs offrent des perspectives intéressantes en terme d'intégrabilité monolithique avec les interrupteurs à semi-conducteurs. L'architecture proposée est constituée de deux transducteurs CMUTs de part et d'autre d'un substrat en silicium. Un outil de modélisation a été développé dans le but de prédire le comportement du transformateur. Des protocoles de mesure du rendement des dispositifs fabriqués ont été mis en place permettant une évaluation quantitative des performances des prototypes (un rendement de 32 % est atteint avec une marge de progression à 60 %). L'exploitation du modèle développé, et validé par les résultats de caractérisation, a permis de mettre en évidence les limites et perspectives d'amélioration de ces dispositifs. / This work is a study of CMUT (Capacitive Micromachined Ultrasonic Transduer)based acoustical transformers as a step in the development of insulating components in semiconductor switches control chain. CMUT transducers being electromechanical systems (MEMS), their monolithic integration with semiconductor switches is full of interesting perspectives . The proposed architecture consists of two CMUTs layered on each side of a silicon substrate. A computational tool was designed to predict the behaviour of the transformer. Measurement protocols of the power efficiency of the constructed transformers were set up and allowed to quantify the prototypes' performances (A 32 % efficiency is currently reached, with improvements attainable up to 60 %). Exploring the results of the developed model, validated by bench measurements, allowed to determine the current limits of the transformers as well as perspectives of improvement.

Les travaux présentés ici proposent des convertisseurs d’énergie à haut rendement et très large dynamique de tension d’entrée, c'est-à-dire capables de fonctionner avec un rendement énergétique élevé sur une plage de tension d’entrée étendue (typiquement de 9V à 200V). De multiples tensions de réseaux sont standards dans l’industrie : elles sont spécifiques à un domaine (aéronautique, ferroviaire, …) et dépendent de la source primaire d’alimentation électrique (batterie d’accumulateurs, génératrice, …). Au sein d’un équipement embarqué, plusieurs réseaux peuvent cohabiter : une alimentation principale 110V et une alimentation de secours sur batterie 12V, par exemple. Le besoin de convertisseurs large dynamique d’entrée est donc une réalité, mais il n’existe sur le marché que peu de convertisseurs capables de réaliser une dynamique d’entrée supérieure à dix. Dans un premier temps, nous avons étudié les enjeux et les problématiques liés à la large dynamique d’entrée, afin de mieux cerner les limitations des topologies de puissance classiques. Nous avons ensuite traité le cas d’une architecture de conversion d’énergie de type série, dont nous avons amélioré le rendement énergétique grâce à l’utilisation de circuits d’aide à la commutation. Cette solution ayant des performances limitées, nous avons proposé de nouvelles architectures de convertisseurs DC/DC, de type parallèle, capables de supporter des dynamiques de tension d’entrée supérieures à vingt et ayant un rendement énergétique élevé (supérieur à 80%). Nous avons également étudié et mis en œuvre des stratégies de commande, numériques et analogiques, permettant de contrôler ces nouvelles topologies complexes. / Power converters are present in virtually every embedded system, but many standards of DC networks exist: the supply voltage is depending on how the power is generated (battery, alternator …) and can range from 12V to more than 115V. When an equipment must comply with a 110V main supply and 12V back-up supply, the use of a wide input voltage range DC/DC converter is mandatory. Since classical switched mode power converters cannot achieve simultaneously high efficiency and wide input voltage range, manufacturers rarely propose DC/DC converters with an input voltage range greater than 10. This work tackles the issue of wide input voltage power conversion. After discussing about designs trade off and problems that stem from a wide input range, we try to improve the overall efficiency of a classical buck-boost converter, by using non dissipative switching-aid circuits. We also proposed a novel two stages power converter capable of dealing with very wide input voltage ranges (more than 20), without a reduction of the power efficiency. Since those new converters are far more difficult to control, some theoretical analysis was performed and some practical tests were done using complex controls laws.

Aquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall. / This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.

The level of Thread-Level Parallelism (TLP), Instruction-Level Parallelism (ILP), and Memory-Level Parallelism (MLP) varies across programs and across program phases. Hence, every program requires different underlying core microarchitecture resources for high performance and/or energy efficiency. Current core microarchitectures are inefficient because they are fixed at design time and do not adapt to variable TLP, ILP, or MLP. I show that if a core microarchitecture can adapt to the variation in TLP, ILP, and MLP, significantly higher performance and/or energy efficiency can be achieved. I propose MorphCore, a low-overhead adaptive microarchitecture built from a traditional OOO core with small changes. MorphCore adapts to TLP by operating in two modes: (a) as a wide-width large-OOO-window core when TLP is low and ILP is high, and (b) as a high-performance low-energy highly-threaded in-order SMT core when TLP is high. MorphCore adapts to ILP and MLP by varying the superscalar width and the out-of-order (OOO) window size by operating in four modes: (1) as a wide-width large-OOO-window core, 2) as a wide-width medium-OOO-window core, 3) as a medium-width large-OOO-window core, and 4) as a medium-width medium-OOO-window core. My evaluation with single-thread and multi-thread benchmarks shows that when highest single-thread performance is desired, MorphCore achieves performance similar to a traditional out-of-order core. When energy efficiency is desired on single-thread programs, MorphCore reduces energy by up to 15% (on average 8%) over an out-of-order core. When high multi-thread performance is desired, MorphCore increases performance by 21% and reduces energy consumption by 20% over an out-of-order core. Thus, for multi-thread programs, MorphCore's energy efficiency is similar to highly-threaded throughput-optimized small and medium core architectures, and its performance is two-thirds of their potential. / text

The demand for low power wireless transceiver implementations has been fueled by multiple applications in the recent decades, including cellular systems, wireless local area networks, personal area networks, biotelemetry and sensor networks. Dynamic range, which is set by linearity and sensitivity performance, is a critical design metric in many of these systems. Both linearity and sensitivity requirements continue to become progressively challenging in many systems due to greater spectrum usage and the need for high data rates respectively. The objective of this research is to investigate power-efficient circuit techniques for reducing the power requirement in receiver front-ends without compromising the dynamic range performance. In the first part of the dissertation, a low power receiver down-converter topology for enhancing dynamic range performance is presented. Current mode down-converters with passive mixer cores have been shown to provide excellent dynamic range performance. However, in contrast to a current commutating Gilbert cell, these down-converters require separate bias current paths for the RF transconductor and the baseband transimpedance amplifier. The proposed topology reduces the power requirement of conventional current mode passive down-converter by sharing the bias current between the transconductance and transimpedance stages. This is achieved without compromising the available voltage headroom for either stage, which is a limitation of bias-sharing based on the use of stacked stages. The dynamic range of the basic bias-current-shared topology is further enhanced through suppression of low frequency noise and IM3 products. Two variants of the down-converter, employing a broadband common-gate and a narrowband common-source input stage, are implemented in a 0.18-μm CMOS technology. The dynamic range performance of the architecture is analyzed. Finally, a prototype of a full direct-conversion receiver implementation with quadrature outputs and integrated LO synthesis is demonstrated. A power-efficient oscillator design for phase noise minimization is presented in the second part of this dissertation. This design is targeted towards multi-radio platforms where several communication links operate simultaneously over multiple frequency bands. Blockers from concurrently operating radios present a major design challenge. The blockers not only make the frontend linearity requirement more stringent but also degrade receiver sensitivity through reciprocal mixing with the phase noise sidebands of LO. Phase noise minimization is thus critical for ensuring high sensitivity in frequency bands where large blockers are present and not sufficiently attenuated by pre-select filters. A capacitive power combining technique in oscillators is introduced to improve phase noise performance. By combining this approach with current reuse, the phase noise is reduced at lower power, compared to conventional LC oscillators. This leads to improved power efficiency. Moreover, the technique mitigates modeling uncertainty arising from phase noise reduction through simultaneous impedance and current scaling. The mode selection in this oscillator, which employs multiple coupled resonators, is analyzed and the impact of coupling on far-out phase noise performance is discussed. Multi-mode oscillation can potentially arise in other oscillator topologies too, e.g., in multiphase oscillators. Mode selection in a widely used transistor-coupled quadrature oscillator is analyzed in detail in the final part of the dissertation. The analysis shows how cross-compression among multiple competing modes can lead to suppression of non-dominant modes in the steady state. / text

Cette thèse se concentre sur l’amélioration conjointe de l'efficacité spectrale et de l'efficacité en puissance de schémas de transmission par satellite. L’émergence de nouveaux services et l'augmentation du nombre d’acteurs dans le domaine nécessitent de disposer de débits de plus en plus importants avec des ressources de plus en plus limitées. Les progrès réalisés ces dernières années sur la technologie embarquée et dans le domaine des communications numériques permettent de considérer des schémas de transmission à plus haute efficacité spectrale et en puissance. Cependant, l’enjeu majeur des schémas de transmission proposes actuellement reste de rentabiliser les ressources disponibles. L’étude développée dans cette thèse explore les possibilités d’amélioration conjointe de l’efficacité spectrale et de l’efficacité en puissance en proposant la combinaison de la modulation Cyclic Code-Shift-Keying (CCSK), dont l’efficacité en puissance augmente avec l’élévation du degré de la modulation, avec une technique de multiplexage par codage de type Code-Division Multiplexing (CDM) pour pallier la dégradation de l’efficacité spectrale liée à l’étalement du spectre induit par la modulation CCSK. Deux approches basées sur l’utilisation de séquences de Gold de longueur N sont définies: Une approche multi-flux avec un décodeur sphérique optimal en réception. La complexité liée à l’optimalité du décodeur conduit à des valeurs d'efficacité spectrale limitées mais l’étude analytique des performances, vérifiée par des simulations, montre une augmentation de l'efficacité en puissance avec l'efficacité spectrale. Une approche mono-flux justifiée par l’apparition de redondance dans les motifs résultant du multiplexage des séquences. L’approche mono-flux propose des valeurs d’efficacité spectrale équivalente aux schémas retenus dans le standard DVB-S2 avec une amélioration de l’efficacité en puissance à partir d’un certain seuil de rapport signal à bruit par rapport à ces schémas. Par la suite, l'étude porte sur la transposition de plusieurs symboles de modulation sur les porteuses d’un système OFDM et sur les bénéfices et avantages d’une telle approche. Elle se conclut sur l’apport d’un codage canal basé sur des codes par bloc non binaires Reed-Solomon et LDPC. La forme d’onde proposée offre des points de fonctionnement à haute efficacité spectrale et haute efficacité en puissance avec des perspectives intéressantes. Dans le contexte actuel, son application reste limitée par ses fluctuations d’amplitude mais est envisageable dans un contexte de transmission multiporteuse, comme attendu dans les années à venir. / This thesis focuses on jointly improving the spectral efficiency and the power efficiency of satellite transmission schemes. The emergence of new services and the increasing number of actors in this field involve higher transmission rates with increasingly limited resources. Recent progress in the embedded technologies and in digital communications offered to consider transmission schemes with higher spectral and power efficiency. Nevertheless, the major current challenge consists in making efficient use of resources. The study developed in this thesis explores the possibilities of jointly improving the spectral and power efficiency by offering a combination of the Cyclic-Code-Shift Keying modulation (CCSK), which power efficiency increases with the degree of modulation, with a multiplexing technique such as Code-Division Multiplexing (CDM) to offset the deterioration on the spectral efficiency due to the spread spectrum induced by CCSK. Two approaches based on the use of Gold sequences of length N are defined : A multi-stream approach with an optimal receiver implemented through sphere decoding. The complexity due to the receiver optimality leads to limited spectral efficiencies but the study of performance, confirmed by simulations, shows an increase in power efficiency with spectral efficiency. A single-stream approach justified by the appearance of redundancy in the patterns following the sequences multiplexing. The single-stream approach offers spectral efficiencies equivalent to the adopted schemes in the DVB-S2 standard, with improved power efficiency from a certain level of signal to noise ratio compared to those schemes. Subsequently, the study focuses on the implementation of several modulation symbols on the subcarriers of an OFDM modulator and the benefits and advantages of such an approach. It concludes with the contribution of channel coding based on nonbinary block codes such as Reed-Solomon and LDPC codes. The proposed waveform offers operating points with high spectral efficiency and high power efficiency with attractive perspectives. In the current context, its application is limited by its amplitude fluctuations but is possible in a multicarrier transmission context, as expected in the years to come.