Widely used design techniques for radio frequency power amplifiers yield results which are approximate; the initial design is usually refined by applying trial-and-error procedures in the laboratory. More accurate design techniques are complicated in their application and have not gained acceptance by practicing engineers. A new design technique for VHF linear power amplifiers using bipolar junction transistors is presented in this report. This design technique is simple in its application but yields accurate results. The design technique is based upon a transistor model which is simple enough to be useful for design, but which is sufficiently accurate to predict performance at high frequencies. Additionally, the model yields insight into many of the processes which take place within the typical RF power transistor. The fundamental aspect of the model is the inclusion of charge storage within the transistor base. This charge storage effect gives rise to a nearly sinusoidal collector current waveform, even in a transistor which ostensibly is biased for class B or nonsaturating class C operation. Methods of predicting transistor input and output impedances are presented. A number of other topics related to power amplifier measurement and design are also included. A unique measurement approach which is ideally suited for use with power amplifiers is discussed. This measurement approach is a hybrid of the common S-parameter measurement technique and the "load-pull" procedure. Practical considerations such as amplifier stability, bias network design, and matching network topology are also included in the report. / Ph. D.

The demand for higher frequency applications is largely driven by bandwidth. The evolution of circuits in the microwave and millimeter frequency ranges always demands higher performance and lower cost as the technology and specification requirements evolve. Thus the development of new processes addressing higher frequencies and bandwidth requirements is essential to the growth of any semiconductor company participating in these markets. There exist processes which can perform in the higher frequency design space from a technical perspective. However, a cost effective solution must complement the technical merits for deployment. Thus a new 0.15 um optical lithography pHEMT process was developed at TriQuint Semiconductor to address this market segment. A 40 GHz power amplifier has been designed to quantify and showcase the capabilities of this new process by leveraging the existing processing knowledge and the implementation of high frequency scalable models. The three stage power amplifier was designed using the TOM4 scalable depletion mode FET model. The TriQuint TQP15 Design Kit also implements microstrip transmission line models that can be used for evaluating the interconnect lines and matching networks. The process also features substrate vias and the thin film resistor and MIM capacitor models which utilize the capabilities of the BCB process flow. During the design stage we extensively used Agilent ADS program for circuit and EM simulation in order to optimize the final design. Special attention was paid to proper sizing of devices, developing matching circuits, optimizing transmission lines and power combining. The final design exhibits good performance in the 40 GHz range using the new TQP15 process. The measured results show a gain of greater than 13 dB under 3 volt drain voltage and a linear output power of greater than 28 dBm at 40 GHz. The 40 GHz power amplifier demonstrates that the new process has successfully leveraged an existing manufacturing infrastructure and has achieved repeatability, high volume manufacturing, and low cost in the millimeter frequency range.

In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers. / A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations. / The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA control functions, it is demonstrated that the method is better positioning GaAs HBT technologies, which are known to offer very competitive RF performances but inherently have limited integration capabilities. / Finally, an analytical approach for the evaluation of inter-modulation distortion (IMD) in envelope feedback architectures is introduced, and the proposed design equations and methodology for IMD analysis may prove very helpful for theoretical analyses, for simulation tasks, and for experimental work.

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Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.