<p>This thesis work investigates the effects of crosstalk on on-chip interconnects. We use optimal repeater insertion as a reference and derive analytical expressions for signal latency, maximum data-rate and power consumption. Through calculations and simulations we show that despite large uncertainties in arrival time of a signal that is subject to crosstalk, we are able to make predictions about the maximum data-rate on a bus. We also show that data-rates can exceed the classical limit of the latency inverted by using wave pipelining. To increase the data-rate, we can increase the number of repeaters to a limit, at the cost of additional latency and power. Savings in power consumption can be achieved by using fewer repeaters, paying in latency and data-rate. Through fewer repeaters, the top metal layer shows better performance in all investigated aspects.</p>

<p>Enhanced packet-data access is a trend in third generation mobile communication system. WCDMA Release 5 introduces HSDPA (High Speed Packet Data Access) with a brand new downlink transport channel HS-DSCH (High Speed Downlink Shared Channel) into 3GPP specification to provide greater capacity. HS-DSCH supports some new feature such as fast link adaptation, fast scheduling and fast HARQ (hybrid ARQ) so as to increase system performance. It efficiently improves power utilization, shortens retransmission time and increases system throughput. </p><p>The focus for this thesis is implementation and simulation of HSDPA functionality with ns-2. There is some previous work has been done, such as EURANE. EURANE is an end to end extension which adds several HSDPA modules to ns-2. This paper addresses the analysis of HSDPA by simulating on HS-DSCH based on EURANE, and extends the power consumption on HS-DSCH.</p>

<p>Nowadays, NRTS (Nighttime Road Traffic Safety) and energy saving are very hot topics in transportation field. This thesis investigates a general optimal model for minimizing NRTAs (nighttime road traffic accidents) and power consumption of the road lighting. To establish this model, the relationship between N/D RTAs (Night to Day Road Traffic Accidents) ratio and road lighting condition and the relationship between power consumption and road lighting condition have been studied and explained. A media variable “economic cost” has been chosen which is used for making a connection between these two relationships. The evaluations of NRTAs and power consumption from cost point of view are introduced as well. The impacts of each internal factor defined by author are explained carefully. The result of the model based on these relationships and internal influencing factors is presented in the paper. Finally, the recommendations for reducing NRTAs and/or power consumption, as well as other interesting areas for further study are presented.</p>

<p>Cell Broadcast (CB) is a possible technical realisation of a global emergency alert system. It is a technique used for sending short text messages to all mobile stations (MSs) in a defined geographical area. An potential effect of using CB is the increase in battery consumption of the MS due to the fact that an extra channel has to be used to make the service available even when the network is otherwise congested. Another part of the service which leads to a potential problem is making CB messages available in different languages. Investigating these problems is the objective of this thesis and the studies it includes. During the first part of the thesis, we measured the battery consumption of MSs in different modes of operation in order to analyse how CB affects the amount of current drained. The tests showed that battery consumption increased only slightly when CB messages were being received at the MS. Although some of the results can be, and are, discussed, we believe that CB would have a small effect on the power consumption of an MS, particularly in a context where it would be used for emergency warning messages only. This mentioned, it would however be wishful to confirm the conclusions further through the realisation of long-term testing. The second part of the thesis deals with the investigation of the MSs’ support for CB messages with different coding schemes. Based on the investigation’s result, we have come to the conclusion that in the long term the usage of different coding schemes on the same channel is preferred. However, the usage of one, global, emergency channel is hard to realise since that requires a standardisation between all countries. In our opinion this may be achieved first in the long run and until then, the usage of separate channels seems to be necessary.</p>

Power consumption is an important constraint in achieving efficient execution on High Performance Computing Multicore Systems. As the number of cores available on a chip continues to increase, the importance of power consumption will continue to grow. In order to achieve improved performance on multicore systems scientific applications must make use of efficient methods for reducing power consumption and must further be refined to achieve reduced execution time. In this dissertation, we introduce a performance modeling framework, E-AMOM, to enable improved execution of scientific applications on parallel multicore systems with regards to a limited power budget. We develop models for each application based upon performance hardware counters. Our models utilize different performance counters for each application and for each performance component (runtime, system power consumption, CPU power consumption, and memory power consumption) that are selected via our performance-tuned principal component analysis method. Models developed through E-AMOM provide insight into the performance characteristics of each application that affect performance for each component on a parallel multicore system. Our models are more than 92% accurate across both Hybrid (MPI/OpenMP) and MPI implementations for six scientific applications. E-AMOM includes an optimization component that utilizes our models to employ run-time Dynamic Voltage and Frequency Scaling (DVFS) and Dynamic Concurrency Throttling to reduce power consumption of the scientific applications. Further, we optimize our applications based upon insights provided by the performance models to reduce runtime of the applications. Our methods and techniques are able to save up to 18% in energy consumption for Hybrid (MPI/OpenMP) and MPI scientific applications and reduce the runtime of the applications up to 11% on parallel multicore systems.

Nowadays, NRTS (Nighttime Road Traffic Safety) and energy saving are very hot topics in transportation field. This thesis investigates a general optimal model for minimizing NRTAs (nighttime road traffic accidents) and power consumption of the road lighting. To establish this model, the relationship between N/D RTAs (Night to Day Road Traffic Accidents) ratio and road lighting condition and the relationship between power consumption and road lighting condition have been studied and explained. A media variable “economic cost” has been chosen which is used for making a connection between these two relationships. The evaluations of NRTAs and power consumption from cost point of view are introduced as well. The impacts of each internal factor defined by author are explained carefully. The result of the model based on these relationships and internal influencing factors is presented in the paper. Finally, the recommendations for reducing NRTAs and/or power consumption, as well as other interesting areas for further study are presented.

This thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.

This thesis work investigates the effects of crosstalk on on-chip interconnects. We use optimal repeater insertion as a reference and derive analytical expressions for signal latency, maximum data-rate and power consumption. Through calculations and simulations we show that despite large uncertainties in arrival time of a signal that is subject to crosstalk, we are able to make predictions about the maximum data-rate on a bus. We also show that data-rates can exceed the classical limit of the latency inverted by using wave pipelining. To increase the data-rate, we can increase the number of repeaters to a limit, at the cost of additional latency and power. Savings in power consumption can be achieved by using fewer repeaters, paying in latency and data-rate. Through fewer repeaters, the top metal layer shows better performance in all investigated aspects.

Enhanced packet-data access is a trend in third generation mobile communication system. WCDMA Release 5 introduces HSDPA (High Speed Packet Data Access) with a brand new downlink transport channel HS-DSCH (High Speed Downlink Shared Channel) into 3GPP specification to provide greater capacity. HS-DSCH supports some new feature such as fast link adaptation, fast scheduling and fast HARQ (hybrid ARQ) so as to increase system performance. It efficiently improves power utilization, shortens retransmission time and increases system throughput. The focus for this thesis is implementation and simulation of HSDPA functionality with ns-2. There is some previous work has been done, such as EURANE. EURANE is an end to end extension which adds several HSDPA modules to ns-2. This paper addresses the analysis of HSDPA by simulating on HS-DSCH based on EURANE, and extends the power consumption on HS-DSCH.

Most discrete time filters use Switched Capacitor structures, but Switched capacitor circuits have finite sampling rate and high power consumption. In this paper we use Switched Current structure to increase sampling rate and reduce power consumption. In this paper, we use a Class-AB structure to compose a double sampling third order low-pass filter. In this paper there are two integrator types. Modified backward Euler and modified forward Euler integrators were realized with double sampling technology from the backward Euler and forward Euler integrators. Compared with other circuits, the circuit has low power supply¡Blow power consumption ¡Bhigh sampling speed. We employ HSPICE and MATLAB to simulate and design the circuit. We use TSMC 0.35£gm process to implement this circuit. The power supply is 1.8V, the cut-off frequency is 3.6MHz, the sampling frequency is 72MHz, and the power consumption is 1.303mW.