Master of Science / This thesis presents an in-depth investigation into the thermal design and optimization of Planar magnetics. With system engineering approach, starting from a two stage DC/DC converter, and further extended to other types of resonant converters with planar core. The study aims to address the thermal challenges associated with these converters, including heat generation, temperature limitations, and cooling solutions, to improve their performance and reliability.

Due to the increasing trend towards energy saving of white goods appliances and the commercial viability of power electronic components, there has been an expansion in the use of solid state electronics and variable frequency drive motors in these applications. However, a major drawback of using such energy efficient loads is the introduction of current harmonics onto the local distribution grid. Furthermore, the proliferation of such devices elevates the harmonic content of the supply voltage and the ensuing potential impact on residential distribution networks. This thesis investigates the harmonic content generated by some representative household appliances and suggests a solution to minimize current harmonics by means of active filtering. An active filter circuit is proposed and simulations will be undertaken to compare filter performance when used as an active front end versus a feeder input compensator. Further, a hardware design of the filter was implemented to experimentally verify the filter operation. / Thesis / Master of Applied Science (MASc)

Almost all electronic devices require efficient conversion of electrical power from one form to another. Electrical power is used world wide at the rate of approximately 12 billion kW per hour. The Center for Power Electronics Systems at Virginia Tech was established with a vision to develop an integrated systems approach via integrated power electronic modules (IPEMs) to improve the reliability, cost-effectiveness, and performance of power electronics systems. IPEMs are multi-layered structures based on embedded power technology and offer the advantage of three-dimensional (3D) packaging of electronic components in a small and compact volume, replacing the traditional wire bonding technology. They have the potential to offer reduced time and effort associated with developing and manufacturing power processors. However, placing multiple heat generating chips in a small volume also makes thermal management more challenging. With the steady increase in the heat density of the electronic packages during the last few decades, thermal management is becoming a key enabling technology for the future growth of power electronics. The focus of this work is on using computational analysis tools and experimental techniques to assess fundamental and practical cooling limitations on IPEMs, developing both passive and active integrated thermal management strategies, and creating design guidelines for IPEMs based on both thermal and thermo-mechanical stress considerations. Specifically, a commercially available finite element package is used to create a 3D geometric layout of the electronic module. The baseline finite element numerical model is validated using bench-top wind tunnel experiments. The experimental setup is also employed to characterize the thermal behavior of chips in the multi-chip package and test the applicability of superposition methodology for temperature fields of chips within multi-chip modules. Using numerical models, both passive and active integrated thermal management strategies are investigated. The passive cooling strategies include advanced ceramic materials, copper trace thickness, and structural enhancements. Active cooling strategies include double-sided cooling using traditional heat sinks, and an extension of double-sided cooling concept using microchannels integrated with the module on both sides of embedded chips. The overall result of the work presented here is the better understanding of thermal issues and limitations with IPEM technology, and development of thermal design guidelines for cooling strategies that take into consideration both thermal and thermo-mechanical performance. / Ph. D.

As is the case for DC-DC converters, multi-phase converters require both high-quality power control and high power-density. Although a higher switching frequency not only improves the quality of the converter output but also decreases the size of the converter, it increases switching losses and electromagnetic interference (EMI) noise. Since the soft-switching topologies reduce the switching losses of the converter main switches, the topologies make converters partially independent from the switching frequency. However, the conventional soft-switching topologies have already proposed most of the possible ways to improve converter performance. In addition, the trends of the newly generated power devices reduce the advantages of soft-switching topologies. This critical situation surrounding soft-switching topologies gives research motivations: What features of soft-switching topologies facilitate their practical applications? Given this motivation, the dissertation discusses two aspects = simplifying auxiliary circuits and accounting for the effects of soft-switching operations on the converter control. Engineers working with medium- and high-power multi-phase converters require simplified soft-switching topologies that have the same level of performance as the conventional soft-switching topologies. This demand is the impetus behind one of the research objectives = simplifying the auxiliary circuits of Zero-Voltage-Transition (ZVT) inverters. Simplifying the auxiliary circuits results in both a smaller number of and lower cost for auxiliary components, without any negative impact on performance. This dissertation proposes two major concepts for the simplification - the Single-Switch Single-Leg (S3L) ZVT cell and the Phase-Lock (PL) concept. Throughout an effort to eliminate circulating currents of inductor-coupled (IC) ZVT converters, the S3L ZVT cell is developed. The proposed cell allows a single auxiliary switch to achieve zero-voltage conditions for both the top and bottom main switches, and it achieves the same level of performance as the conventional ZVT cell, as well. This proposal makes IC ZVT topologies more attractive to multi-phase converter applications. Because all of the top main switches generally have identical sequences for zero-voltage turn-on commutations, one auxiliary switch might handle the commutations of all of the top main switches. This possibility introduces the PL concept, which allows the two auxiliary switches to provide a zero-voltage condition for any main switch commutation. In order to compensate for restrictions of this concept, a modified space-vector modulation (SVM) scheme also is introduced. A soft-switching topology changes the duty ratios of the converter, which affects the controllability of the converter. Therefore, this dissertation selects resolution of this issue as one of the research objectives. This dissertation derives the generalized timing equations of ZVT operations, and the generalized equations formulize the effect of ZVT operation on both duty ratios and DC current. Moreover, the effect of SVM schemes is also investigated. An average model of the ZVT converter is developed using both the timing analysis and the investigation of SVM schemes, and small-signal analysis using the average model predicts the steady-state characteristics of the converter. / Ph. D.

This thesis analyzes the procedural approach and benefits of applying optimization techniques to the design of a boost power factor correction (PFC) converter with an input electromagnetic interference (EMI) filter at the component level. The analysis is performed based on the particular minimum cost design study of a 1.15 kW unit satisfying a set of specifications. A traditional design methodology is initially analyzed and employed to obtain a first design. A continuous design optimization is then formulated and solved to gain insight into the converter design tradeoffs and particularities. Finally, a discrete optimization approach using a genetic algorithm is defined to develop a completely automated user-friendly software design tool able to provide in a short period of time globally optimum designs of the system for different sets of specifications. The software design tool is then employed to optimize the system design, and the savings with respect to the traditional design methodology are highlighted. The optimization problem formulation in both the continuous and discrete cases is presented in detail. The system design variables, objective function (system component cost) and constraints are identified. The objective function is expressed as a function of the design variables. A computationally efficient and experimentally validated model of the system, including second-order effects, allows the constraint values (also as a function of the design variables) to be obtained. / Master of Science

For many years, power electronics in the high-power area was performed with extremely slow semiconductor switches. These switches, including the thyristor and the Gate Turn-Off (GTO) thyristor, had the capacity to handle very high voltages and currents but lacked the ability to perform high frequency switching. Low-power converters, such as computer power supplies and low horsepower motor drives, have employed high-frequency switching for years and have benefited from very nice output waveforms, good control dynamic performance, and many other advantages compared to low frequency switching. Recent improvements in high-power semiconductor technology has brought switching performance similar to that of the low-power MOSFETs and IGBTs to the high-power area through the advancement of the IGBT's ratings to create the High Voltage IGBT (HVIGBT) and the development of new GTO-derived devices including the Integrated Gate Commutated Thyristor (IGCT) and the Emitter Turn-Off (ETO) thyristor. These new devices all feature high switching speed and the capability to turn off without the requirement for a turn-off snubber. With these new device technologies the high-power field of power electronics can realize dramatic improvements in the performance of systems for utility applications and motor drives. However, with these high-speed switches come new issues relating to noise, protection, performance of diodes, and thermal management in high-frequency applications. This thesis addresses the application of these new devices, especially the ETO and the IGCT. Examples of each device technology (IGBT, IGCT, and ETO) have been characterized in both their switching performance and conduction loss. The tests performed show how these new devices may be applied to various applications. The switching loss, especially related to turn-off, is the dominant factor in the power dissipation of the high-power switches, so knowledge of these characteristics are very important in the system design. To demonstrate the operation of the ETO, two power converters were constructed. The first was a 100 kW DC/DC converter, which demonstrated the operation of the ETO in a typical building block configuration, the half-bridge. The second system, a 1 MegaVolt-Amp (MVA) three-phase inverter, demonstrated the ETO in an application where the switching frequency and power level were both high. The test results demonstrate the expected characteristics of the high-frequency converters. The development of the ETO's gate driver is described. During the inverter testing, a new failure mode was found involving a parasitic diode within the ETO. This failure mode was analyzed and solutions were proposed. One of the proposed solutions was implemented and there were no more failures of this type. Another possible failure mode regarding a circulating current in an IGCT-based system is also analyzed. Soft-switching techniques can help reduce the switching loss in power semiconductor switches. Several topologies were considered for application in the high-power area, and one was selected for further investigation. A prototype Zero Current Transition (ZCT) circuit was developed using an IGCT as the main switch. The turn-off loss was reduced dramatically through the tested ZCT circuit, and the diode recovery was also alleviated. / Master of Science

Variable Frequency Drives (VFDs) are utilized in commercial and industrial facilities to improve motor efficiency and provide process flexibility. VFDs are nonlinear loads that inject harmonic currents into the power system, and result in harmonic voltages across the system impedance. This harmonic distortion can negatively impact the performance of other sensitive loads in the system. If a VFD serves a critical function, it may be necessary to supply the VFD from a Diesel Generator or Uninterruptible Power Supply (UPS). These sources have relatively high impedance when compared to a standard utility source, and will result in greater harmonic voltage distortion. This increases the likelihood of equipment failure due to harmonics. The full extent of the impact, however, is typically unknown until an extensive harmonic analysis is performed or the system is installed and tested. This thesis evaluates the impact that source impedance has on the harmonic voltage distortion that is produced by nonlinear loads such as VFDs. An ideal system of varying source types (Utility, Generator and UPS) and varying VFD rectifier technologies (6-Pulse, 12-Pulse and 18-Pulse) is created to perform this analysis and plot the results. The main output of this thesis is a simplified methodology for harmonic analysis that can be implemented when designing a power system with a VFD serving a critical function and a high impedance source like a generator or UPS. Performing this analysis will help to ensure that other sensitive loads will operate properly in the system. / Master of Science

This research explores two issues when implementing drain-source voltage sensed synchronous rectification (SR) on LLC DC-Transformers (DCXs). Firstly, a current resonance issue caused by the SR controller, and secondly a early turn-off issue from parasitics present in the drain-source sensing path. Two novel methods are proposed to solve the early turn-off issue, and an FPGA based solution is built to validate and fix the resonance issue. Simulations are run to quantify the amount of rectifier power savings possible with the proposed solutions. / Master of Science / This research explores issues and improvements in synchronous rectifiers used in resonant based power conversion circuits. The two issues explored hurt rectifier efficiency, and thus total power conversion circuit efficiency. Implementation issues are identified, simulated, and new solutions are proposed. Simulations are run to quantify the amount of power savings is possible.

Development of Power Electronic Building Block (PEBB) modules, initiated through the Office of Naval Research (ONR), is a promising enabling technology which will promote future electrical power systems. Key in this development is the thermal design of a PEBB packaging scheme that will manage the module's high heat dissipation levels. As temperatures in electronics are closely associated with operating efficiency and failure rates, management of thermal loads is necessary to ensure proper and reliable device performance. The current work investigates the thermal design requirements for a preliminary PEBB module developed by the NSF Center for Power Electronics Systems (CPES) at Virginia Tech. This module locates four primary heat-generating devices onto a copper bonded substrate in a multi-chip module format. The thermal impact of several design variables (including heat sink quality, substrate material, device spacing, and substrate and metallization thickness) are modeled within the multi-layer thermal analysis software TAMSä. Model results are in the form of metal layer surface temperatures that closely represent the device junction temperatures. Other design constraints such as electrical and material characteristics are also considered in the thermal design. Design results indicate for the device heat dissipation levels that a low resistance heat sink coupled with a high conductivity substrate, such as aluminum nitride, are required for acceptable device junction temperatures. Substrate performance, in the form of a spreading resistance component, will be negatively affected by a lower quality heat sink. Both forced air and cold plate cooling methods were found acceptable; factors such as environment, cost and integration will determine which solution is most feasible. Maximum surface temperatures can be lowered somewhat through adjustment of device spacing. However, this reduction was small compared to the impact on parasitic capacitance. Additionally, there is some thermal benefit to thicker high-conductivity substrates, whereas lower conductivity substrates will increase the maximum surface temperature. Thicker copper layers will prove beneficial though this benefit is not as great for higher conductivity substrates. Also discussed are the on-going and future development efforts that are expected to require thermal consideration. These consist of a top-level thermal bus for additional heat removal, the use of metal matrix composites and concepts for multi-module integration. / Master of Science

M.Ing. / Please refer to full text to view abstract