Today's state-of-the-art rate vibratory gyroscopes use a large proof mass that vibrates at a low resonance frequency (3-30 kHz), a condition that creates a performance tradeoff in which the gyroscope can either offer large bandwidth or high resolution, but not both. This tradeoff led to the development of the capacitive bulk acoustic wave (BAW) silicon disk gyroscope, a new class of micromachined rate vibratory gyroscopes operating in the frequency range of 1-10MHz with high device bandwidth and shock/vibration tolerance. By scaling the frequency, BAW gyroscopes can provide low mechanical noise without sacrificing the high bandwidth performance needed for most commercial applications. The drive loop of the BAW gyroscope can also be exploited as a timing device that can be integrated in existing commercial systems to provide competitive clock performance to the state-of-the-art using less area and power. This dissertation discusses the design and implementation of a CMOS ASIC architecture that interfaces with a high-Q, wide-bandwidth BAW gyroscope and the challenges associated with optimizing the noise performance to achieve navigation-grade levels of sensitivity as the frequency is scaled into the MHz regime. Mathematical models are derived to describe the operation of the sensor and are used to generate equivalent electrical circuit models of the gyroscope. A design strategy is then outlined for the ASIC to optimize the drive loop and sense channel for power and noise, and steps toward reducing this noise as the system is pushed to navigation-grade performance are presented that maintain optimum system power consumption. After analyzing the BAW gyroscope and identifying a strategy for developing the drive and sense interface circuitry, a complete fully-differential ASIC is designed in 0.18μm CMOS to interface with a bulk acoustic wave (BAW) disk gyroscope. As an oscillator, the gyroscope provides an uncompensated clock signal at ~9.64 MHz with a temperature sensitivity of -27 ppm/°C and phase noise of -104 dBc at 1 kHz from carrier. When the complete ASIC is interfaced with the gyroscope, the sensor shows a measured rate sensitivity of 1.15 mV/o/s with an open-loop bandwidth of 280 Hz and a bias instability of 0.095 o/s, suitable for the rate-grade performance commonly required for commercial and consumer electronics applications. The system is recorded to have a total power of 1.6 mW and a total area of 0.64 mm2. Following the design of the interface ASIC, this dissertation investigates in further detail the requirements for designing and optimizing charge pumps for capacitive MEMS devices. Basic charge pump design is outlined, followed by an overview of techniques that can be used to generate larger polarization voltages from the ASIC. Lastly, an alternate measurement technique for measuring the rotation rate of the gyroscope is discussed. This technique is based on the phase-shift modulation of the gyroscope output signal when the device is driven with two orthogonal signal inputs and can be easily modified to provide either linear scale factor measurement or a linear calibration curve that can be used to track and adjust the variation of the sensor scale factor over time.

We study current-induced domain wall dynamics in a thin ferromagnetic nanowire. We derive the effective equations of domain wall motion, which depend on the wire geometry and material parameters. We describe the procedure to determine these parameters by all-electric measurements of the time-dependent voltage induced by the domain wall motion. We provide an analytical expression for the time variation of this voltage. Furthermore, we show that the measurement of the proposed effects is within reach with current experimental techniques. We also show that a certain resonant time-dependent current moving a domain wall can significantly reduce the Joule heating in the wire, and thus it can lead to a novel proposal for the most energy efficient memory devices. We discuss how Gilbert damping, non-adiabatic spin transfer torque, and the presence of Dzyaloshinskii-Moriya interaction can effect this power optimization. Furthermore, we propose a new nanodot magnetic device. We derive a specific time-dependent current that is needed to switch the magnetization of the nanodot the most efficiently.

Submitted by Felipe Fakir null (zafakir@yahoo.com.br) on 2017-06-27T07:01:28Z No. of bitstreams: 1 FFAKIR Dissertação vFinalFichaCataAta.pdf: 2064786 bytes, checksum: 158a935a636b9dbf9e59618a35b4c8ef (MD5) / Approved for entry into archive by Luiz Galeffi (luizgaleffi@gmail.com) on 2017-06-28T19:39:58Z (GMT) No. of bitstreams: 1 fakir_f_me_bauru.pdf: 2064786 bytes, checksum: 158a935a636b9dbf9e59618a35b4c8ef (MD5) / Made available in DSpace on 2017-06-28T19:39:58Z (GMT). No. of bitstreams: 1 fakir_f_me_bauru.pdf: 2064786 bytes, checksum: 158a935a636b9dbf9e59618a35b4c8ef (MD5) Previous issue date: 2017-06-01 / A tecnologia de comunicação wireless vem se tornando parte fundamental do cotidiano das indústrias de processos, onde o uso de transmissores wireless aplicados à monitoração e controle já é uma realidade. A arquitetura de Sistema de Controle via Rede Sem Fio (WNCS) possui vantagens em relação às arquiteturas tradicionais ponto-a-ponto e às arquiteturas de redes cabeadas devido à facilidade de instalação, configuração e manutenção. No entanto, a evolução desta tecnologia introduziu novos desafios para a implementação da malha de controle fechada por um instrumento wireless como as não linearidades, perda de pacote de dados e restrições da comunicação de dados nas redes sem fio. Outro fator crítico relacionado à implementação de WNCSs é a fonte de energia limitada destes transmissores, que possuem vida útil dependente da quantidade de acessos e dados transmitidos. Este trabalho apresenta o estudo e o desenvolvimento de um controlador preditivo multi-rate como alternativa para melhorar a eficiência energética em aplicações industriais de WNCSs. A estratégia proposta não necessita receber constantemente os valores reais das variáveis do processo transmitidos pelos transmissores wireless, pois o controlador preditivo baseado em modelo (MPC) se utiliza do submodelo interno das variáveis de processo para estimar os valores das variáveis quando estas não são transmitidas. Dessa forma, uma diminuição da frequência de transmissão de dados na rede sem fio pode ser obtida e, consequentemente uma redução do consumo energético dos dispositivos sem fio. Resultados de simulações em diferentes condições de operação de um WNCS multivariável de controle de tanques acoplados demonstram que o MPC multi-rate possui características de robustez e é efetivo para aplicações de WNCS, garantindo requisitos de controle e estabilidade mesmo com a diminuição da frequência de transmissão de dados de realimentação na rede sem fio. Adicionalmente, resultados do consumo energético dos dispositivos do WNCS mostraram que o MPC multi-rate proporciona uma economia de energia de até 20% das baterias dos transmissores wireless. Uma análise da eficiência energética do WNCS é apresentada através do estudo dos limites operacionais do controlador MPC multi-rate considerando a relação de compromisso entre o período de amostragem dos dispositivos sem fio e o desempenho de controle do WNCS. / Wireless communication technology has become a fundamental part of the everyday life of process industries, where the use of wireless transmitters for monitoring and control is already a reality. The architecture of Wireless Networked Control Systems (WNCSs) has advantages over point-to-point and wired networks architectures due to the ease of installation, configuration and maintenance. However, the evolution of this technology has introduced new challenges to the implementation of the closed loop control with a wireless instrument as nonlinearities, packet losses and data communication constraints in the wireless networks. Another critical factor related to implementation of WNCSs is the energy source of these transmitters, which have limited lifetime dependent on the amount of access and data transmitted. This work presents the study and the development of a multi-rate predictive controller as an alternative to improve energy efficiency in industrial applications of WNCSs. The proposed strategy does not need to frequently receive updated process variables transmitted by wireless transmitters, because the model predictive controller (MPC) uses the internal submodel of the process variables to estimate the variables values when they are not transmitted. Thus, a decrease in the frequency of data transmission on the wireless network can be obtained and consequently a reduction of energy consumption of wireless devices. Simulation results for different operating conditions of a multivariable WNCS of coupled tanks shows that the multi-rate MPC provides robustness and it is effective for WNCS applications, ensuring control and stability requirements even with the reduction of the transmission frequency of the feedback data in the wireless network. In addition, energy consumption results from the WNCS devices showed that MPC multi-rate provides 20% of energy economy as it is effective in saving the energy expenditure of the wireless transmitter’s battery. An energy efficiency analysis of the WNCS is presented by studying the operating limits of the multi-rate MPC controller considering the compromise relationship between the sampling period of the wireless devices and the control performance of the WNCS.

No description available.

This masters thesis is dealing with energetic evaluation of selected municipal WWTP – WWTP Polička. First chapter, introduction explains basic terms and goals of thesis. Second chapter explains energy audit, energy audit process its scope and contents. Third chapter deals with assesing life cycle using LCA (life cycle assesment). Fourth chapter deal with energy consumption at WWTP in Czech Republic as well as in the world. Fifth chapter describes technology of WWTP Polička and its fundamental objects. Sixth chapter is assesment of WWTP Polička from hydraulic point of view and assesment of selected machinery. Further there is summation of capital and operational costs followed by capital investment return.

Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajuster, outre les paramètres usuels que sont la tension d'alimentation et la fréquence d'horloge, la tension de body bias. C'est dans ce contexte que ce travail étudie les nouvelles possibilités offertes et explore des solutions innovantes de gestion dynamique de la tension d'alimentation, fréquence d'horloge et tension de body bias afin d'optimiser la consommation énergétique des systèmes sur puce. L'ensemble des paramètres tensions/fréquence permettent une multitude de points de fonctionnement, qui doivent satisfaire des contraintes de fonctionnalité et de performance. Ce travail s'intéresse donc dans un premier temps à une problématique de conception, en proposant une méthode d'optimisation du placement de ces points de fonctionnement. Une solution analytique permettant de maximiser le gain en consommation apporté par l'utilisation de plusieurs points de fonctionnement est proposée. La deuxième contribution importante de cette thèse concerne la gestion dynamique de la tension d'alimentation, de la fréquence et de la tension de body bias, permettant d'optimiser l'efficacité énergétique en se basant sur le concept de convexité. La validation expérimentale des méthodes proposées s'appuie sur des échantillons de circuits réels, et montre des gains en consommation moyens allant jusqu'à 35%. / Beyond 28nm CMOS BULK technology node, some limits have been reached in terms of performance improvements. This is mainly due to the increasing power consumption. This is one of the reasons why new technologies have been developed, including those based on Silicon-On-Insulator (SOI). Moreover, the standardization of complex architectures such as multi-core architectures emphasizes the problem of power management at fine-grain. FD-SOI technologies offer new power management opportunities by adjusting, in addition to the usual parameters such as supply voltage and clock frequency, the body bias voltage. In this context, this work explores new opportunities and searches novel solutions for dynamically manage supply voltage, clock frequency and body bias voltage in order to optimize the power consumption of System on Chip.Adjusting supply voltage, frequency and body bias parameters allows multiple operating points, which must satisfy the constraints of functionality and performance. This work focuses initially at design time, proposing a method to optimize the placement of these operating points. An analytical solution to maximize power savings achieved through the use of several operating points is provided. The second important contribution of this work is a method based on convexity concept to dynamically manage the supply voltage, the frequency and the body bias voltage so as to optimize the energy efficiency. The experimental results based on real circuits show average power savings reaching 35%.

Les Réseaux de capteurs sans fil (WSN) sont une technologie émergente avec des applications potentielles dans divers domaines de la vie quotidienne, tels que la surveillance structurelle et environnementale, la médecine, la surveillance militaire, les explorations robotisées, etc. Les nœuds de capteurs doivent fonctionner pendant une longue période avec des batteries capacité limitée, par conséquent le facteur plus important dans les WSN est la consommation d'énergie. Dans cette thèse, nous proposons des techniques d'optimisation algorithmiques dynamiques, et adaptative pour la réduction de l'énergie. Tout d'abord, un modèle énergétique précis est présenté. Ce modèle repose sur des mesures réelles de courant consommé pour différents scénarios qui peuvent se produire lors de la communication entre les nœud. Il en est conclu que la couche MAC joue un rôle essentiel dans la réduction de l'énergie consommée. Ensuite, un protocole MAC dynamique est présenté. Il adapte de manière dynamique l’intervalle de réveil des nœuds de capteurs à partir d’une estimation du trafic. L’algorithme adaptatif modélisé de façon heuristique pour comprendre le comportement de convergence des paramètres algorithmiques. Le protocole est appliqué sur des réseaux de capteurs corporels et il surclasse les autres protocoles MAC en termes de latence ainsi que de consommation d'énergie ce qui permet donc d'augmenter la durée de vie de trois à six fois. Enfin, une technique basée sur l’optimisation adaptative de la puissance d'émission radio est appliquée sur des canaux variant dans le temps. La puissance de sortie est réglée dynamiquement au meilleur niveau de puissance selon l’état du canal, ce qui diminue la consommation d’un facteur deux. / Wireless Sensor Networks (WSN) are a fast emerging technology with potential applications in various domains of daily-life, such as structural and environmental monitoring, medicine, military surveillance, robotic explorations etc. WSN devices are required to operate for a long time with limited battery capacity, therefore, the most important constraint in WSN is energy consumption. In this thesis, we propose algorithmic-level dynamic and adaptive optimization techniques for energy reduction in WSN. First, an accurate energy model is presented. This model relies on real-time power measurements of various scenarios that can occur during communication between sensor nodes. It is concluded that MAC layer plays a pivotal role for energy reduction. Then, a traffic-aware dynamic MAC protocol is presented which dynamically adapts the wake-up schedule of sensor nodes through traffic estimation. An adaptive algorithm is designed for this purpose that is heuristically modeled to understand the convergence behavior of algorithmic parameters. The proposed protocol is applied to body area networks and it outperforms other low-power MAC protocols in terms of latency as well as energy consumption and consequently increases the lifetime from three to six times. Finally, an SNR-based adaptive transmit power optimization technique is applied under time-varying channels. The output power is dynamically tuned to best power level under slow varying channel, which results in an average gain by two times.

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, therby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniatrurization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse and limits the usability of clustered architectures in smaller technologies. In the past, study of leakage energy management at the architectural level has mostly focused on storage structures such as cache. Relatively, little work has been done on architecture level leakage energy management in functional units in the context of superscalar processors and energy efficient scheduling in the context of VLIW architectures. In the absence of any high level model for interconnect energy estimation, the primary focus of research in the context of interconnects has been to reduce the latency of communication and evaluation of various inter-cluster communication models. To the best of our knowledge, there has been no such work in the past from the point of view of enegy efficiency targeting clustered VLIW architectures specifically focusing on smaller technologies. Technological advancements now permit design of interconnects and functional units With varying performance and power modes. In thesis we people scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low power modes of interconnects and functional units . We also propose a high level model for estimation of interconnect delay and energy (in contrast to low-level circuit level model proposed earlier) that makes it possible to carry out architectural and compiler optimizations specifically targeting the inter connect, Finally we present synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improve the usability of clustered architectures by archiving better overall energy-performance trade-offs. Our compiler assisted leakage energy management scheme for functional units reduces the energy consumption of functional units approximately by 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively with negligible performance degradation over and above that offered by a hardware-only scheme. The interconnect energy optimization scheme improves the energy consumption of interconnects on an average by 41% and 46% for a 2-clustered and a 4-clustered machine respectively with 2% and 1.5% performance degradation. The combined scheme options slightly better energy benefit in functional units and 37% and 43% energy benefit in interconnect with slightly higher performance degradation. Even with the conservative estimates of contribution of functional unit interconnect to overall processor energy consumption the proposed combined scheme obtains on an average 8% and 10% improvement in overall energy delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine respectively. We present a detailed experimental evaluation of the proposed schemes using the Trimaran compiler infrastructure.

The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip cache has become very significant. We explore various techniques to switch-off the over-allocated cache so as to reduce leakage power consumed by it. A large cache offers non-uniform access latency to different cores present on a CMP and such a cache is called “Non-Uniform Cache Architecture (NUCA)”. Past studies have explored techniques to reduce leakage power for uniform access latency caches and with a single application executing on a uniprocessor. Our ideas of power optimized caches are applicable to any memory technology and architecture for which the difference of leakage power in the on-state and off-state of on-chip cache bank is significant. Switching off the last level shared cache on a CMP is a challenging problem due to concurrently executing threads/processes and large dispersed NUCA cache. Hence, to determine cache requirement on a CMP, first we propose a new highly accurate method to estimate working set size of an application, which we call “tagged working set size estimation (TWSS)” method. This method has a negligible hardware storage overhead of 0.1% of the cache size. The use of TWSS is demonstrated by adaptively adjusting cache associativity. Our ideas of adaptable associative cache is scalable with respect to the number of cores present on a CMP. It uses information available locally in a tile on a tiled CMP and thus avoids network access unlike other commonly used heuristics such as average memory access latency and cache miss ratio. Our implementation gives 25% and 19% higher EDP savings than that obtained with average memory access latency and cache miss ratio heuristics on a static NUCA platform (SNUCA), respectively. Cache misses increase with reduced cache associativity. Hence, we also propose to map some of the L2 slices onto the rest L2 slices and switch-off mapped L2 slices. The L2 slice includes all L2 banks in a tile. We call this technique the “remap policy”. Some applications execute with lesser number of threads than available cores during their execution. In such applications L2 slices which are farther to those threads are switched-off and mapped on-to L2 slices which are located nearer to those threads. By using nearer L2 slices with the help of remapped technology, some applications show improved execution time apart from reduction in leakage power consumption in NUCA caches. To estimate the maximum possible gains that can be obtained using the remap policy, we statically determine the near-optimal remap configuration using the genetic algorithms. We formulate this problem as a energy-delay product minimization problem. Our dynamic remap policy implementation gives energy-delay savings within an average of 5% than that obtained with the near-optimal remap configuration. Energy-delay product can also be minimized by improving execution time, which depends mainly on the static and dynamic NUCA access policies (DNUCA). The suitability of cache access policy depends on data sharing properties of a multi-threaded application. Hence, we propose three indices to quantify data sharing properties of an application and use them to predict a more suitable cache access policy among SNUCA and DNUCA for an application.

The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip cache has become very significant. We explore various techniques to switch-off the over-allocated cache so as to reduce leakage power consumed by it. A large cache offers non-uniform access latency to different cores present on a CMP and such a cache is called “Non-Uniform Cache Architecture (NUCA)”. Past studies have explored techniques to reduce leakage power for uniform access latency caches and with a single application executing on a uniprocessor. Our ideas of power optimized caches are applicable to any memory technology and architecture for which the difference of leakage power in the on-state and off-state of on-chip cache bank is significant. Switching off the last level shared cache on a CMP is a challenging problem due to concurrently executing threads/processes and large dispersed NUCA cache. Hence, to determine cache requirement on a CMP, first we propose a new highly accurate method to estimate working set size of an application, which we call “tagged working set size estimation (TWSS)” method. This method has a negligible hardware storage overhead of 0.1% of the cache size. The use of TWSS is demonstrated by adaptively adjusting cache associativity. Our ideas of adaptable associative cache is scalable with respect to the number of cores present on a CMP. It uses information available locally in a tile on a tiled CMP and thus avoids network access unlike other commonly used heuristics such as average memory access latency and cache miss ratio. Our implementation gives 25% and 19% higher EDP savings than that obtained with average memory access latency and cache miss ratio heuristics on a static NUCA platform (SNUCA), respectively. Cache misses increase with reduced cache associativity. Hence, we also propose to map some of the L2 slices onto the rest L2 slices and switch-off mapped L2 slices. The L2 slice includes all L2 banks in a tile. We call this technique the “remap policy”. Some applications execute with lesser number of threads than available cores during their execution. In such applications L2 slices which are farther to those threads are switched-off and mapped on-to L2 slices which are located nearer to those threads. By using nearer L2 slices with the help of remapped technology, some applications show improved execution time apart from reduction in leakage power consumption in NUCA caches. To estimate the maximum possible gains that can be obtained using the remap policy, we statically determine the near-optimal remap configuration using the genetic algorithms. We formulate this problem as a energy-delay product minimization problem. Our dynamic remap policy implementation gives energy-delay savings within an average of 5% than that obtained with the near-optimal remap configuration. Energy-delay product can also be minimized by improving execution time, which depends mainly on the static and dynamic NUCA access policies (DNUCA). The suitability of cache access policy depends on data sharing properties of a multi-threaded application. Hence, we propose three indices to quantify data sharing properties of an application and use them to predict a more suitable cache access policy among SNUCA and DNUCA for an application.