Small size, light weight, high efficacy, longer lifetime and controllable output are the main advantages of high-frequency electronic ballasts for gas discharge lamps. However, power line quality and electromagnetic interference (EMI) issues arise when a simple peak rectifying circuit is used. To suppress harmonic currents and improve power factor, input-current-shaping (ICS) or power-factor-correction (PFC) techniques are necessary. This dissertation addresses advanced high-frequency electronic ballasting techniques by using a single-stage PFC approach. The proposed techniques include single-stage boost-derived PFC electronic ballasts with voltage-divider-rectifier front ends, single-stage PFC electronic ballasts with wide range dimming controls, single-stage charge-pump PFC electronic ballasts with lamp voltage feedback, and self-oscillating single-stage PFC electronic ballasts. Single-stage boost-derived PFC electronic ballasts with voltage-divider-rectifier front ends are developed to solve the problem imposed by the high boost conversion ratio required by commonly used boost-derived PFC electronic ballast. Two circuit implementations are proposed, analyzed and verified by experimental results. Due to the interaction between the PFC stage and the inverter stage, extremely high bus-voltage stress may exist during dimming operation. To reduce the bus voltage and achieve a wide-range dimming control, a novel PFC electronic ballast with asymmetrical duty-ratio control is proposed. Experimental results show that wide stable dimming operation is achieved with constant switching frequency. Charge-pump (CP) PFC techniques utilize a high-frequency current source (CS) or voltage source (VS) or both to charge and discharge the so-called charge-pump capacitor in order to achieve PFC. The bulky DCM boost inductor is eliminated so that this family of PFC circuits has the potential for low cost and small size. A family of CPPFC electronic ballasts is investigated. A novel VSCS-CPPFC electronic ballast with lamp-voltage feedback is proposed to reduce the bus-voltage stress. This family of CPPFC electronic ballasts are implemented and evaluated, and verified by experimental results. To further reduce the cost and size, a self-oscillating technique is applied to the CPPFC electronic ballast. Novel winding voltage modulation and current injection concepts are proposed to modulate the switching frequency. Experimental results show that the self-oscillating CS-CPPFC electronic ballast with current injection offers a more cost-effective solution for non-dimming electronic ballast applications. / Ph. D.

Les conditionneurs alternatifs – continu à absorption sinusoïdale (PFC) pour les applications critiques se distinguent par un haut niveau de performances tel que les THD réduits, un haut rendement et une bonne fiabilité. Leur importance est d’autant plus nécessaire qu’une continuité de service des alimentations est requise même en présence d’une défaillance interne de composant. Deux types de structures associées à leur commande sont réalisés à cet effet, les structures à redondance parallèle et les structure à redondance en série. Elles consistent respectivement en l’ajout d’un bras d’interrupteur dans le cas de la redondance parallèle, qui est une option plus compliquée et en une suppression d’une cellule de commutation dans le deuxième cas. L’étude présentée ici, consiste en premier lieu en une exploration et une évaluation de nouvelles familles de topologies multi-niveaux, caractérisée par un partitionnement cellulaire en série. Ces nouvelles topologies, ainsi que leurs variantes, comportent au moins une redondance structurelle avec des cellules mono-transistor à défaut de commande non critique et symétriques à point-milieu. Elles sont donc génériques pour la mise en parallèle et l’extension en triphasé. Cependant, elles sont pour la plupart peu compétitives à cause des composants qui sont souvent surdimensionnés et donc plus onéreuses, en comparaison avec la structure PFC Double-Boost 5 Niveaux à composants standards 600 V (brevetée par l’INPT – LAPLACE –CNRS en 2008) que nous étudions. Cette dernière constitue le meilleur compromis entre un bon rendement et une maîtrise des contraintes en mode dégradé. Sur le plan théorique nous montrons que le seul calcul de fiabilité basé uniquement sur un critère de premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globale sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé de PFC double-boost 5 niveaux à commande entièrement numérique et à MLI optimisée reconfigurable en temps réelle a été réalisé afin de valider l’étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis 3 niveaux par exemple. Ce prototype a également servi de test d'endurance aux transistors CoolMos et diodes SiC volontairement détruits dans des conditions d'énergie maîtrisée et reproductibles. D’autres campagnes d'endurance en modes dégradés ont été réalisées en laboratoire sur plusieurs centaines d’heures en utilisant ce même prototype. Nous nous sommes axés sur la détection de défauts internes et le diagnostic (localisation) rapide, d'une part par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par la détection d’harmoniques (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. Enfin, nous proposons une nouvelle variante PFC expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorable que la structure brevetée. / This work is an exploration and an evaluation of new variants of multi-level AC/DC topologies (PFC) considering their global reliability and availability: electrical safety with an internal failure and post-failure operation. They are based on a non-differential AC and centre tap connection that led to symmetrical arrangement cells in series. These topologies permit an intrinsic active redundancy between cells in a same group and a segregation capability between the two symmetrical groups of cells. More again, they are modular and they can be paralleled and derived to any number of levels. Only single low-voltage (600V) transistor pear cell is used avoiding the short-circuit risk due to an unwanted control signal. Comparisons, taking into account losses, distribution losses, rating and stresses (overvoltage and over-temperature) during the post-operation are presented. Results highlight the proposed 5-level Double-Boost Flying Capacitor topology. This one was patented at the beginning of thesis, as a solution with the best compromise. On the theoretical side, we show that the reliability calculation based only on a "first fault occurrence" criterion is inadequate to really describe this type of topology. The inclusion of fault tolerance capability is needed to evaluate the overall reliability law (i.e. including a second failure). The adaptation of theoretical models with constant failure rate including overvoltage and over-temperature dependencies exhibit an increasing of the reliability over a short time. This property is an advantage for embedded systems with monitoring condition. Local detection and rapid diagnosis of an internal failure were also examined in this work. Two methods are proposed firstly, by a direct flying caps monitoring and secondly, by a realtime and digital synchronous demodulation of the input sampled voltage at the switching frequency (magnitude and phase). Both techniques have been integrated on FPGA and DSP frame and evaluated on a AC230V-7kW DC800V – 31kHz lab. set-up. We put forward the interest of the second method which only uses one input voltage sensor. Finally, we propose in this dissertation a new generic X-level PFC Vienna using, in 5-level version, half transistors and drivers for identical input frequency and levels. At the cost of a slight increase of losses and density losses, this topology appears very attractive for the future. A preliminary lab. set-up and test were also realized and presented at the end of the thesis.

This thesis deals with the reactive power compensation, namely the possibility of reactive power compensation in Petrochemie company using a passive power factor correction system instead of synchronous generators, as part of the contract Kompel company. The thesis analyzes problems of definition of power in circuits with sinusoidal and nonsinusoidal voltages and currents. Furthermore, this thesis describes the power factor correction systems used in the low and medium voltage industrial and distribution networks. The last four chapters contain description of the existing state of power plant in Petrochemie company. There are considered the possibility of use of existing power factor correction system owned by company. The new static power factor correction system is suggested and functionality of power factor correction systems is verified through the simulations.

"In this thesis, based on the existing researches on power factor correction technology, I analyze, design and study the Boost type power factor correction technology, which is applied in the in-board two-stage battery charger. First I analyzed the basic working principle of the active power factor corrector. By comparing several different topologies of PFC converter main circuit and control methods, I specified the research object to be the average current control (ACM) boost power factor corrector. Then I calculated and designed the PFC circuit and the ACM controller applied in the first level charging of EVs. And I run the design in Simulink and study the important features like power factor, the input current waveform and the output DC voltage and the THD and odd harmonic magnitude."

This thesis mainly presents the design and implementation of a flyback converter with single-stage power factor correction. In the beginning, we propose different power factor collection (PFC) techniques referring to the inductor current of converter under three kinds of operation modes. In the continuous mode, we adopt the nonlinear-carrier control (NLC). Then, in the discontinuous mode and boundary mode, voltage-follower control (VFC) and transition mode technique control (TM) are adopted respectively. As to the converter analysis, we derive and verify the results of a small-signal model and perform equivalent circuit analysis by state-space averaging method, loss-free resistor (LFR) model, averaging method for two-time-scale system (AM), and current injected equivalent circuit approach (CIECA). Results derived from the above-mentioned models are compared and verified to be accurate of the system model. Furthermore, the control function and element design are implemented by simulation. We perform a PI controller to achieve better power factor based on results of analysis of the time and frequency domains analysis. Finally, three sets of different hardware are fabricated and verified depending on measured result and theoretical simulation.

This study aims to design a Shunt Semi-Active Power Factor Correction Circuits , which can be applied to high power circuit by low switching frequency. The designed circuit can avoid power loss working with high switching frequency when using the method of active power factor correction .The experimental configuration based on DSP is applied to a compressor of air conditioner with varied load. The simulation check the developed circuit using Ispice . Both of the experimental and simulation results have guaranteed the derived configuration reach the expected goals.

This thesis presented a sensor-less permanent magnet synchronous motor (PMSM) driver for controlling air-conditioner rotary compressor speed. In this thesis, a quasi-sine pulse-width modulation (PWM) driving method was proposed. Furthermore, the current feedback control scheme and rotor magnet pole position detection were included. The system structure was implemented by using a digital signal processing (DSP) platform. The proposed driving scheme was compared with the square-wave driving without current feedback and six-step square-wave driving method with current feedback. Moreover, the passive and shunt semi-active power factor correction (PFC) technique were researched for the air-conditioner application. Experimental results demonstrated that the system power factor could be improved by the proposed shunt semi-active PFC method. Besides, the proposed sensor-less quasi-sine PWM driving method implemented in an air-conditioner compressor driver was capable of reducing the magnitude of rotational speed ripples, compressor vibration, and system power consumption.

The traditional AC/DC rectifier usually results in low power factor and serious harmonic distortion and it will bring about the serious pollution to power system. This thesis proposes boost power factor correction technique to solve these problems. First, we aim at power factor correction circuit which need input voltage sensing, to study its operating principle and design consideration, then design applicable voltage compensator by the frequency analysis and perform the simulation and implementation using the developed criterion. In order to prevent the shortcoming that power factor correction circuits with input voltage sensing and complexity is raised for a multiplier must be added to controller, we develop the power factor correction circuit without input voltage sensing. We perform the operating principle and control function by simulation, develop hardware scheme by analog components and place load variation to measure power factor and total harmonic distortion. According to experimental results and simulation, we confirm the new power factor correction circuit. When the full load is placed, the power factor can achieve 0.99 and the total harmonic distortion is lower than 8%.

A single-stage high-power-factor electronic ballast is designed for fluorescent lamps with dimming capability. The circuit configuration is originated from the integration of the half-bridge resonant inverter and the buck-boost converter. The buck-boost converter is designed to operate in discontinuous conduction mode (DCM) to provide nearly unit power factor at a fixed switching frequency. With asymmetrical pulse-width-modulation (APWM), the lamp power can be effectively regulated. The power switches of the inverter exhibit either zero-voltage-switching (ZVS) or zero-current-switching (ZCS) over the whole dimming range. Design equations are derived and computer analyses are performed based on a power-dependent lamp model and fundamental approximation. Design guidelines for determining circuit parameters are provided. A prototype circuit for a T8-36W fluorescent lamp is built and tested to verify the analytical predictions.

In this thesis, an alternative solution for designing power line conductive electromagnetic interference (EMI) filter by using the consecutive orthogonal array method is proposed. The circuit parameters of EMI filters to be determined are assigned as the control variables in the orthogonal arrays, and the average effects corresponding to each control variable are calculated from the measured results. In accordance with the inferential rules, the average effects are used as the observational indices to adjust the levels of the control variables of the subsequent orthogonal array. Through manipulating consecutive orthogonal arrays step by step, the applicable ranges of circuit parameters are approached with desired output performances. Finally, the component values of EMI filters with minimum size can be found. The design procedure and the inferential rules are described by illustrative examples for a single-stage high-power-factor converter.