Chu-Keung Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (leaves 88-92). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Structure of the Thesis --- p.4 / Chapter 2 --- Literature Review --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Complete Algorithms --- p.7 / Chapter 2.2.1 --- Parallel Checking --- p.7 / Chapter 2.2.2 --- Mom's --- p.8 / Chapter 2.2.3 --- Davis-Putnam --- p.9 / Chapter 2.2.4 --- Nonchronological Backtracking --- p.9 / Chapter 2.2.5 --- Iterative Logic Array (ILA) --- p.10 / Chapter 2.3 --- Incomplete Algorithms --- p.11 / Chapter 2.3.1 --- GENET --- p.11 / Chapter 2.3.2 --- GSAT --- p.12 / Chapter 2.4 --- Summary --- p.13 / Chapter 3 --- Algorithms --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Tree Search Techniques --- p.14 / Chapter 3.2.1 --- Depth First Search --- p.15 / Chapter 3.2.2 --- Forward Checking --- p.16 / Chapter 3.2.3 --- Davis-Putnam --- p.17 / Chapter 3.2.4 --- GRASP --- p.19 / Chapter 3.3 --- Incomplete Algorithms --- p.20 / Chapter 3.3.1 --- GENET --- p.20 / Chapter 3.3.2 --- GSAT Algorithm --- p.22 / Chapter 3.4 --- Summary --- p.23 / Chapter 4 --- Field Programmable Gate Arrays --- p.24 / Chapter 4.1 --- Introduction --- p.24 / Chapter 4.2 --- FPGA --- p.24 / Chapter 4.2.1 --- Xilinx 4000 series FPGAs --- p.26 / Chapter 4.2.2 --- Bitstream --- p.31 / Chapter 4.3 --- Giga Operations Reconfigurable Computing Platform --- p.32 / Chapter 4.4 --- Annapolis Wildforce PCI board --- p.33 / Chapter 4.5 --- Summary --- p.35 / Chapter 5 --- Implementation --- p.36 / Chapter 5.1 --- Parallel Graph Coloring Machine --- p.36 / Chapter 5.1.1 --- System Architecture --- p.38 / Chapter 5.1.2 --- Evaluator --- p.39 / Chapter 5.1.3 --- Finite State Machine (FSM) --- p.42 / Chapter 5.1.4 --- Memory --- p.43 / Chapter 5.1.5 --- Hardware Resources --- p.43 / Chapter 5.2 --- Serial Graph Coloring Machine --- p.44 / Chapter 5.2.1 --- System Architecture --- p.44 / Chapter 5.2.2 --- Input Memory --- p.46 / Chapter 5.2.3 --- Solution Store --- p.46 / Chapter 5.2.4 --- Constraint Memory --- p.47 / Chapter 5.2.5 --- Evaluator --- p.48 / Chapter 5.2.6 --- Input Mapper --- p.49 / Chapter 5.2.7 --- Output Memory --- p.49 / Chapter 5.2.8 --- Backtrack Checker --- p.50 / Chapter 5.2.9 --- Word Generator --- p.51 / Chapter 5.2.10 --- State Machine --- p.51 / Chapter 5.2.11 --- Hardware Resources --- p.54 / Chapter 5.3 --- Serial Boolean Satisfiability Solver --- p.56 / Chapter 5.3.1 --- System Architecture --- p.58 / Chapter 5.3.2 --- Solutions --- p.59 / Chapter 5.3.3 --- Solution Generator --- p.59 / Chapter 5.3.4 --- Evaluator --- p.60 / Chapter 5.3.5 --- AND/OR --- p.62 / Chapter 5.3.6 --- State Machine --- p.62 / Chapter 5.3.7 --- Hardware Resources --- p.64 / Chapter 5.4 --- GSAT Solver --- p.65 / Chapter 5.4.1 --- System Architecture --- p.65 / Chapter 5.4.2 --- Variable Memory --- p.65 / Chapter 5.4.3 --- Flip-Bit Vector --- p.66 / Chapter 5.4.4 --- Clause Evaluator --- p.67 / Chapter 5.4.5 --- Adder --- p.70 / Chapter 5.4.6 --- Random Bit Generator --- p.71 / Chapter 5.4.7 --- Comparator --- p.71 / Chapter 5.4.8 --- Sum Register --- p.71 / Chapter 5.5 --- Summary --- p.71 / Chapter 6 --- Results --- p.73 / Chapter 6.1 --- Introduction --- p.73 / Chapter 6.2 --- Parallel Graph Coloring Machine --- p.73 / Chapter 6.3 --- Serial Graph Coloring Machine --- p.74 / Chapter 6.4 --- Serial SAT Solver --- p.74 / Chapter 6.5 --- GSAT Solver --- p.75 / Chapter 6.6 --- Summary --- p.76 / Chapter 7 --- Conclusion --- p.77 / Chapter 7.1 --- Future Work --- p.78 / Chapter A --- Software Implementation of Graph Coloring in CHIP --- p.79 / Chapter B --- Density Improvements Using Xilinx RAM --- p.81 / Chapter C --- Bit stream Configuration --- p.83 / Bibliography --- p.88 / Publications --- p.93

Tsoi Kuen Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 84-92). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.3 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background and Review --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Cryptographic Algorithms --- p.6 / Chapter 2.3 --- Cryptographic Applications --- p.10 / Chapter 2.4 --- Modern Reconfigurable Platforms --- p.11 / Chapter 2.5 --- Review of Related Work --- p.14 / Chapter 2.5.1 --- Montgomery Multiplier --- p.14 / Chapter 2.5.2 --- IDEA Cipher --- p.16 / Chapter 2.5.3 --- RC4 Key Search --- p.17 / Chapter 2.5.4 --- Secure Random Number Generator --- p.18 / Chapter 2.6 --- Summary --- p.19 / Chapter 3 --- The IDEA Cipher --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- The IDEA Algorithm --- p.21 / Chapter 3.2.1 --- Cipher Data Path --- p.21 / Chapter 3.2.2 --- S-Box: Multiplication Modulo 216 + 1 --- p.23 / Chapter 3.2.3 --- Key Schedule --- p.24 / Chapter 3.3 --- FPGA-based IDEA Implementation --- p.24 / Chapter 3.3.1 --- Multiplication Modulo 216 + 1 --- p.24 / Chapter 3.3.2 --- Deeply Pipelined IDEA Core --- p.26 / Chapter 3.3.3 --- Area Saving Modification --- p.28 / Chapter 3.3.4 --- Key Block in Memory --- p.28 / Chapter 3.3.5 --- Pipelined Key Block --- p.30 / Chapter 3.3.6 --- Interface --- p.31 / Chapter 3.3.7 --- Pipelined Design in CBC Mode --- p.31 / Chapter 3.4 --- Summary --- p.32 / Chapter 4 --- Variable Radix Montgomery Multiplier --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- RSA Algorithm --- p.34 / Chapter 4.3 --- Montgomery Algorithm - Ax B mod N --- p.35 / Chapter 4.4 --- Systolic Array Structure --- p.36 / Chapter 4.5 --- Radix-2k Core --- p.37 / Chapter 4.5.1 --- The Original Kornerup Method (Bit-Serial) --- p.37 / Chapter 4.5.2 --- The Radix-2k Method --- p.38 / Chapter 4.5.3 --- Time-Space Relationship of Systolic Cells --- p.38 / Chapter 4.5.4 --- Design Correctness --- p.40 / Chapter 4.6 --- Implementation Details --- p.40 / Chapter 4.7 --- Summary --- p.41 / Chapter 5 --- Parallel RC4 Engine --- p.42 / Chapter 5.1 --- Introduction --- p.42 / Chapter 5.2 --- Algorithms --- p.44 / Chapter 5.2.1 --- RC4 --- p.44 / Chapter 5.2.2 --- Key Search --- p.46 / Chapter 5.3 --- System Architecture --- p.47 / Chapter 5.3.1 --- RC4 Cell Design --- p.47 / Chapter 5.3.2 --- Key Search --- p.49 / Chapter 5.3.3 --- Interface --- p.50 / Chapter 5.4 --- Implementation --- p.50 / Chapter 5.4.1 --- RC4 cell --- p.51 / Chapter 5.4.2 --- Floorplan --- p.53 / Chapter 5.5 --- Summary --- p.53 / Chapter 6 --- Blum Blum Shub Random Number Generator --- p.55 / Chapter 6.1 --- Introduction --- p.55 / Chapter 6.2 --- RRNG Algorithm . . --- p.56 / Chapter 6.3 --- PRNG Algorithm --- p.58 / Chapter 6.4 --- Architectural Overview --- p.59 / Chapter 6.5 --- Implementation --- p.59 / Chapter 6.5.1 --- Hardware RRNG --- p.60 / Chapter 6.5.2 --- BBS PRNG --- p.61 / Chapter 6.5.3 --- Interface --- p.66 / Chapter 6.6 --- Summary --- p.66 / Chapter 7 --- Experimental Results --- p.68 / Chapter 7.1 --- Design Platform --- p.68 / Chapter 7.2 --- IDEA Cipher --- p.69 / Chapter 7.2.1 --- Size of IDEA Cipher --- p.70 / Chapter 7.2.2 --- Performance of IDEA Cipher --- p.70 / Chapter 7.3 --- Variable Radix Systolic Array --- p.71 / Chapter 7.4 --- Parallel RC4 Engine --- p.75 / Chapter 7.5 --- BBS Random Number Generator --- p.76 / Chapter 7.5.1 --- Size --- p.76 / Chapter 7.5.2 --- Speed --- p.76 / Chapter 7.5.3 --- External Clock --- p.77 / Chapter 7.5.4 --- Random Performance --- p.78 / Chapter 7.6 --- Summary --- p.78 / Chapter 8 --- Conclusion --- p.81 / Chapter 8.1 --- Future Development --- p.83 / Bibliography --- p.84

Typescript (photocopy). / Digitized by Kansas Correctional Industries

投影機相機(projector camera)系統近年相當流行，主要原因是它能夠靈活地展示影像，使用戶有更大的自由度作出操作。手提式投影機的技術在過往幾年急速發展、漸見成熟，知名的家用電子産品生産廠閱始推出内置迷你投影機的手機和攝影機。另一方面手機的運算能力正急劇地提升，它們多都配置不同種類且功能强大的周邊設備。 / 本論文提出並討論一種基於現場可编程邏輯閘陣列(Field Programmable Gate Array, FPGA),並適用於嵌入式系统的特殊處理器。該特殊處理器專門處理來自相機的資料串流，透過一系列的象素圖像處理運算如圖像梯度和高斯模糊，去找出相中物件的邊緣，藉此分擔微處器在運算上的負擔。實驗結果明這特殊處理器可實現於低端的FPGA上並和普遍的微處器一起運作。 / 本論文第二個探討的主題是一個利用多模卡爾曼濾波器(Multiple Model Kalman Filter)的直線追踪器，並利用多個直線追踪器去作投影面板的追踪。利用卡爾曼濾波器只需要很低的運算能力的優點,我們的直線追踪器在嵌入式系统實測時能達到每秒200幀的速度。多模卡爾曼濾波器在實驗中有滿意的成績並較單卡爾曼濾波器和擴展卡爾曼濾波器優異。 / Projector-camera (ProCam in short) systems are getting very popular since the user can change the display area dynamically and enjoy more freedom in handling the device. In recent years, the mobile projector technology is becoming mature and manufacturers are shipping mobile phones and digital cameras with projectors. On the other hand, the computation power of a cell phone had dramatically increased and the cell phones are accompanied with large number of powerful peripherals. / In this thesis, the possibility of making an embedded Projector-camera (ProCam) system is investigated. A ProCam system is developed by our research group previously and designed for desktop Personal Computers(PCs). The system uses computer vision techniques to detect a white cardboard as the projection screen and uses particle filter to trace the screen in subsequent frames. The system demands a large computation power, unfortunately the power of low cost embedded system is still not powerful enough to implement the ProCam system.Therefore, specially designed hardware and computationally efficient algorithm are required in order to implement the ProCam system on an embedded system. / An FPGA based special processor to share the workload of the microcontroller in the embedded system is proposed and tested. This special processor will take the data stream of the camera as the inputs and apply pixel-wise image operators such as image gradient and Gaussian blur in order to extract the edge pixels. As a result, the workload of the microcontroller in the embedded system is reduced. The experiments show that the design can be implement on a low-end FPGA with a simple microcontroller. / A line tracker using Multiple Model Kalman lter is also proposed in this thesis. The aim of this tracker is to reduce the time on tracking the board. Benet from the low computation requirement of Kalman filter, the proposed line tracker can run in 200 fps on our testing embedded system. The experiments also show that the robustness of the Multiple Model Kalman filter is satisfactory and it outperforms the line trackers using single Kalman filter or extended Kalman filter alone. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Fung, Hung Kwan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 115-124). / Abstracts also in Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Objective --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Thesis Organization --- p.5 / Chapter 2 --- Background --- p.7 / Chapter 2.1 --- Introduction --- p.7 / Chapter 2.2 --- Projector-Camera System --- p.8 / Chapter 2.2.1 --- Static Projector-Screen --- p.9 / Chapter 2.2.2 --- Dynamic Projector-Screen --- p.13 / Chapter 2.3 --- Embedded Vision --- p.15 / Chapter 2.4 --- Summary --- p.25 / Chapter 3 --- System Overview --- p.26 / Chapter 3.1 --- System Design --- p.26 / Chapter 3.2 --- Our Approach --- p.28 / Chapter 3.2.1 --- Projector-camera system --- p.28 / Chapter 3.2.2 --- Smart Camera --- p.31 / Chapter 3.2.3 --- Quadrangle Detection and Tracking Module --- p.32 / Chapter 3.2.4 --- Projection Module --- p.32 / Chapter 3.3 --- Extension --- p.33 / Chapter 4 --- Smart Camera --- p.34 / Chapter 4.1 --- Introduction --- p.34 / Chapter 4.2 --- Hardware Overview --- p.35 / Chapter 4.3 --- Image Acquisition --- p.40 / Chapter 4.4 --- Image Processing --- p.42 / Chapter 4.4.1 --- RGB-to-Gray Conversion Module . --- p.44 / Chapter 4.4.2 --- Image Smoothing Module --- p.45 / Chapter 4.4.3 --- Image Gradient Module --- p.49 / Chapter 4.4.4 --- Non-maximum Suppression and Hysteresis Thresholding --- p.53 / Chapter 4.5 --- Summary --- p.55 / Chapter 5 --- Quadrangle Detection and Tracking --- p.57 / Chapter 5.1 --- Introduction --- p.57 / Chapter 5.2 --- Line Feature Extraction --- p.61 / Chapter 5.3 --- Automatic Quadrangle Detection --- p.62 / Chapter 5.4 --- Real-time Quadrangle Tracking --- p.68 / Chapter 5.4.1 --- Line Tracker --- p.69 / Chapter 5.5 --- Tracking Lose Strategy --- p.76 / Chapter 5.6 --- Recover from Tracking Failure --- p.77 / Chapter 5.7 --- Summary --- p.77 / Chapter 6 --- Implementation and Experiment Result --- p.79 / Chapter 6.1 --- Introduction --- p.79 / Chapter 6.2 --- Smart Camera --- p.79 / Chapter 6.3 --- Line Tracking --- p.87 / Chapter 7 --- Limitation and Discussion --- p.101 / Chapter 7.1 --- Introduction --- p.101 / Chapter 7.2 --- Limitation --- p.101 / Chapter 7.3 --- Summary --- p.105 / Chapter 8 --- Application --- p.107 / Chapter 8.1 --- Introduction --- p.107 / Chapter 8.2 --- Portable Projector-Camera System --- p.107 / Chapter 8.3 --- Summary --- p.110 / Chapter 9 --- Conclusion --- p.112 / Bibliography --- p.115

L'évolution des technologies, les exigences de productivité, l'accroissement de la complexité des circuits intégrés ont contribué à l'émergence des composants virtuels (IPs), ainsi qu'au développement de logiciels d'aide à la conception de circuits intégrés. L'utilisation de l'abstraction et des composants déjà conçus sont les clés deces défis.<br />L'objet de cette thèse est le parcours des principaux niveaux d'abstraction de la synthèse matérielle, la synthèse logique, RTL et comportementale, en dégageant pour chacun d'entre eux les contraintes de conception qui vont devenir les critères de sélection d'un bloc réutilisable. il ne reste qu'à concevoir un éventail de blocs dans une approche de réutilisation: les blocs doivent être facilement sélectionnables, puis paramétrables, et enfin intégrables dans un circuit plus important. La conception des blocs comportementaux, appliquée au codage coorecteur d'erreur, nous amène à réfléchir sur les méthodologies de conception et de réutilisation des composants virtuels.

No description available.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 63-71).

Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more robust physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in burst mode, and can reliably synchronize to different QAM constellations burst-by-burst. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers.

FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.

No description available.