Modern Field-Programmable Gate Arrays (FPGAs) can accommodate complex system-on-chip designs and require extensive intellectual-property (IP) support. However, current IP protection mechanisms in FPGAs are limited, and do not reach beyond whole-design bitstream encryption. This work presents an architecture and protocol for securing IP based designs in programmable platforms. The architecture is reprsented by the Secure Authentication Module (SAM), an enabler for next-generation intellectual-property exchange in complex FPGAs. SAM protects hardware, software, application data, and also provides mutual assurances for the end-user and the intellectual-property developer. Further, this work demonstrates the use of SAM in a secure video messaging device on top of a Virtex-II Pro development system. / Master of Science

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The content of this paper is putting forward an idea that applies the software radio technique to the subcarrier demodulation of frequency divided multiplexing telemetry system. Firstly, the article explains the basic thought and application of the software radio. It introduces the main function and the use of the programmable downconverter in HSP50214/ HSP50216. Secondly, it discusses the merit and shortcoming about the method of the subcarrier demodulation of frequency divided multiplexing telemetry system in common use. Finally, the article aims at ± 7.5% proportion bandwidth FM subcarrier channels that in common use in the military standard, introducing HSP50214/HSP50216 programmable downconverter in achievement of design and simulation result. The main problems in the design are discussed and a conclusion obtained.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / The design and development of user interfaces for telemetry data processing systems is undergoing a period of rapid change. The migration to graphics workstations is raising expectations and redefining requirements for user interfaces in the nineties. User interfaces which present data in crude tabular form on alphanumeric terminals are on a path to extinction. Modem telemetry user interfaces are hosted on graphics workstations rich with power and software tools. This paper summarizes the evolution of user interfaces for telemetry systems developed by Computer Sciences Corporation, highlighting key enhancements and use of third-party software. The benefits of prototyping and the trend toward programmable interface behavior are explored.

published_or_final_version / Industrial and Manufacturing Systems Engineering / Doctoral / Doctor of Philosophy

This work is the result of the definition, design and evaluation of a novel method to interconnect the computational elements - commonly known as Configurable Analogue Blocks (CABs) - of a programmable analogue array. This method is proposed for total or partial replacement of the conventional methods due to serious limitations of the latter in terms of scalability. With this method, named Asynchronous Spike Event Coding (ASEC) scheme, analogue signals from CABs outputs are encoded as time instants (spike events) dependent upon those signals activity and are transmitted asynchronously by employing the Address Event Representation (AER) protocol. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. On-line, programmable computation is intrinsic to ASEC scheme and is performed without additional hardware. The ability of the communication scheme to perform computation enhances the computation power of the programmable analogue array. The design methodology and a CMOS implementation of the scheme are presented together with test results from prototype integrated circuits (ICs).

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / The MicroDAS-1000 is an airborne Data Acquisition System (DAS) designed to meet the growing needs of airframe manufacturers for extensive test data accumulation, processing and evaluation. As such, the system has been designed with emphasis on modularity, miniaturization and ease of operator usage and expansion. The MicroDAS product line includes a series of components used as building blocks to configure systems of virtually any size. The modular design of these components allows considerable latitude to the instrumentation engineer in configuring systems for simple or complex applications. The modular concept has been extended to the design of plug-in modules for different functional requirements and system applications. All units are under software control to allow rapid reconfiguration and setup as requirements for instrumentation and data gathering change.

Approved for public release; distribution is unlimited / The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout. / http://archive.org/details/designofmultiple00koyo / Major, Republic of Korea Air Force

M.Ing.

Tendências recentes em redes definidas por software têm estendido a programabilidade de rede para o plano de dados através de linguagens de programação como P4. Infelizmente, a chance de introduzir bugs na rede também aumenta significativamente nesse novo contexto. Para prevenir bugs de violarem propriedades de rede, as técnicas de imposição e verificação podem ser aplicadas. Enquanto imposição procura monitorar ativamente o plano de dados para bloquear violações de propriedades, verificação visa encontrar bugs assegurando que o programa satisfaz seus requisitos. Abordagens de verificação de plano de dados existentes que são capazes de modelar programas P4 apresentam restrições severas no conjunto de propriedades que podem ser verificadas. Neste trabalho, nós propomos ASSERT-P4, uma abordagem de verificação de programas de plano de dados baseada em asserções e execução simbólica. Programadores de rede anotam programas P4 com asserções expressando propriedades gerais de corretude. Os programas anotados são transformados em modelos C e todos os seus caminhos possíveis são executados simbolicamente. Como execução simbólica é conhecida por possuir desafios de escalabilidade, nós também propomos um conjunto de técnicas que podem ser aplicadas neste domínio para tornar a verificação factível. Nomeadamente, nós investigamos o efeito das seguintes técnicas sobre o desempenho da verificação: paralelização, otimizações de compilador, limitações de pacotes e fluxo de controle, estratégia de reporte de bugs, e fatiamento de programas. Nós implementamos um protótipo para estudar a eficácia e eficiência da abordagem proposta. Nós mostramos que ela pode revelar uma ampla gama de bugs e defeitos de software, e é capaz de fazer isso em menos de um minuto considerando diversas aplicações P4 encontradas na literatura. Nós mostramos como uma seleção de técnicas de otimização em programas mais complexos pode reduzir o tempo de verificação em aproximadamente 85 por cento. / Recent trends in software-defined networking have extended network programmability to the data plane through programming languages such as P4. Unfortunately, the chance of introducing bugs in the network also increases significantly in this new context. To prevent bugs from violating network properties, the techniques of enforcement or verification can be applied. While enforcement seeks to actively monitor the data plane to block property violations, verification aims to find bugs by assuring that the program meets its requirements. Existing data plane verification approaches that are able to model P4 programs present severe restrictions in the set of properties that can be verified. In this work, we propose ASSERT-P4, a data plane program verification approach based on assertions and symbolic execution. Network programmers annotate P4 programs with assertions expressing general correctness properties. The annotated programs are transformed into C models and all their possible paths are symbolically executed. Since symbolic execution is known to have scalability challenges, we also propose a set of techniques that can be applied in this domain to make verification feasible. Namely, we investigate the effect of the following techniques on verification performance: parallelization, compiler optimizations, packet and control flow constraints, bug reporting strategy, and program slicing. We implemented a prototype to study the efficacy and efficiency of the proposed approach. We show it can uncover a broad range of bugs and software flaws, and can do it in less than a minute considering various P4 applications proposed in the literature. We show how a selection of the optimization techniques on more complex programs can reduce the verification time in approximately 85 percent.

As the sizes of modern circuit designs become bigger and bigger, implementing those large circuits into FPGA become arduous. The state-of-the-art academic FPGA place-and-route tool, VPR, has good quality but needs around a whole day to complete a placement when the input circuit netlist contains millions of lookup tables, excluding the runtime needed for routing. / To speed up the placement process, we propose a routability-driven placement algorithm for FPGAs, which adopts techniques used in ASIC global placer. Our placer follows the lower-bound-and-upper-bound iterative optimization process in ASIC placers like Ripple. The total half perimeter wirelength (HPWL) of the circuit is used as the objective cost function and it modeled using the Bound2Bound net model. In lower bound computation, a placement solution with the minimum HPWL is determined by the conjugate gradient method. In upper bound computation, an almost-legalized result is produced by spreading cells linearly in the whole placement area. Those positions are then served as fixed-point anchors and fed into the next lower bound computation. Furthermore, global routing will be performed in the upper bound computation to estimate the routing segments usage, as a mean to consider congestion in the placement. The two bounds computations are computed alternatively until their results converge. / We tested our approach using 20 MCNC benchmarks and 16 large benchmarks for performance and scalability. Experimental results show that based on the island-style architecture which VPR is most optimized, our approach can obtain a placement result 8× faster than VPR with 2% more in channel width, or 3× faster with 1% more in channel width when considering congestion either. Our approach is even 20× faster in placing large benchmarks having over 50,000 lookup tables, however, with 10% more in channel width. Based on the Xilinx Virtex-5 architecture from a recent related work, we can out-perform VPR by reducing the channel width by 3% with almost 3× speedup in runtime. / 現今的電路設計得愈來愈大，要把這些巨大的電路實現在現場可程式邏輯門陣列(FPGA)上變得愈來愈困難，由其在布局及布線程序上變得十分耗時。儘管在一般的情況下，現時在學術領域中，最先進的用在FPGA上的布局及布線工具能夠提供高質素的布局結果，但當所需要布局的電路所包含的邏輯元件數達到數百萬個以上時，該工具也要耗費一整天的時間才能完成整個布局程序，其中並未計算之後布線程序所額外需要的時間。 / 有見及此，我們參考了一些應用在特殊應用積體電路(ASIC)設計軟體上的布局方法，並提出了一個專為FPGA而設的偏向優化Routability的布局算法來縮短布局程序所需要的時間。我們的算法以Bound2Bound模型來模擬電路內邏輯元件間的接線，並估算其Half-Perimeter線長(HPWL)來作為我們的目標函數進行優化。我們採用了一些ASIC布局軟體，如Ripple內的上限及下限交互計算的迭代優化程序。在下限的運算過程中，我們在無視節點重疊的情況下，使用了共軛梯度法來找出HPWL的最少值。在上限的運算過程中，我們把在下限計算找到的結果平均散佈在整個可布局的區域內，從而減少節點重疊的情況來得出一接近有效的布局結果。接著，這些節點的位置會被用作定點錨，附加在下一次的下限計算中，並引導它得出一節點重疊相對較少的布局結果。此外，我們可以選擇在上限的運算過程中加入Global Routing程序來估計該布局結果所需的線段數，從而在布局過程中考慮布線過份擁塞的情況。上限及下限的計算會不斷交互進行，直至雙方所得的結果聚合為止。 / 我們使用了20個MCNC基準電路及16個大型基準電路，來測試我們的布局算法的性能和可擴展性。實驗結果指出，針對島狀結構的FPGA，我們的算法能夠比VPR快8倍得出布局結果，但其通道寬度(Channel Width)卻增加了2%。如果在考慮布線擁塞度的情況下，我們的算法能夠比VPR快3倍，但其通道寬度卻增加了1%。再者，對於一些擁有超過50000個邏輯元件的大型基準電路，相比於VPR，雖然我們的算法能夠提供20倍的速度增長，但其布局結果的通道寬度卻增加了10%。如果我們使用在最近的相關研究中使用的Xilinx Virtex-5結構的話，我們的算法能夠比VPR快接近3倍得出布局結果，並且減少約3%的通道寬度。 / Lam, Ka Chun. / Thesis M.Phil. Chinese University of Hong Kong 2014. / Includes bibliographical references (leaves 64-70). / Abstracts also in Chinese. / Title from PDF title page (viewed on 12, October, 2016). / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only.