Thesis (M.S.)--Florida State University, 2004. / Advisor: Dr. Uwe Meyer-Baese, Florida State University, College of Engineering, Dept. of Electrical and Computer Engineering. Title and description from dissertation home page (viewed Sept. 15, 2005). Document formatted into pages; contains ix, 108 pages. Includes bibliographical references.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2005. / Includes bibliographical references (p. 81-86).

Thesis (Ph. D.)--Drexel University, 2005. / Includes abstract and vita. Includes bibliographical references (leaves 120-128).

Thesis (M.S.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on June 25, 2010). Bibliography: leaves 93-96.

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 73-76). Also available on the World Wide Web.

University, Diss., 2003--Saarbrücken.

abstract: There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied extensively. One of the most promising technologies being developed is the resistive RAM (ReRAM). In ReRAM the resistance of the device varies with the voltage applied across it. Programmable metallization cells (PMC) is one of the devices belonging to this category of non-volatile memories. In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation. A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

L'ingénierie des modèles (IDM) a depuis très largement démontré sa pertinence dans les développements logiciels; restait alors à démontrer son applicabilité dans le développement de tout système d'information. Aujourd'hui, de nombreuses expérimentations montrent avec plus ou moins de succès que l'IDM peut parfaitement supporter d'autres domaines comme le domaine du co-design ou celui de l'ingénierie des processus.Dans le domaine du co-design, les activités de conception consiste essentiellement à concevoir et analyser des systèmes implantées sur des plateformes spécifiques (SoC, MPSoC, NoC, etc.): cela nécessite l'utilisation de langages dédiés permettant de représenter : les constituants du système ou de la plateforme, les contraintes non fonctionnelles, les allocations spatio-temporelles des blocs du système sur la plateforme, les analyses qui découlent des choix d'allocation. Le langage de modélisation généraliste UML (Unified Modeling Language) ne pouvait que très difficilement satisfaire de tels besoins. C'est pourquoi l'OMG (Object Management Group) a standardisé une extension d'UML dédiée à la conception et l'analyse de systèmes embarqués temps réel (MARTE). L'objectif premier de cette thèse est de proposer une méthodologie de conception de SoPC (System-on-Programmable-Chip) basée sur l'utilisation de modèles qui fait la synthèse des approches proposées par les communautés de l'ESL et de l'IDM.Aussi avons-nous poussé la réflexion sur les manières de capitaliser au mieux notre méthodologie et sur sa mise en œuvre dans l'élication des processus de co-design. C'est la raison pour laquelle, après avoir fait une étude sur la formalisation des processus de développement, nous avons trouvé opportun de proposer notre propre extension du langage SPEM (Software and System Process Engineering Modeling), standardisé par l'OMG, afin d'y intégrer des concepts manquants, essentiels à notre sens à la représentation des processus IDM de co-design. / The relevancy of the Model Based Approach (MBE) applied in the field of software engineering has been widely demonstrated though several experiments. In the field of co-design, business activities are mainleny design and analysis activities of complex systems implemented into chips (SoC - System-on-Chip) or reprogrammable chip (SoPC) - System-on-Programmable-Chip). Those activities require dedicated languages and tools allowing capture of : system or platform components, non-functional properties, allocation of system blocks onto the platform, either into space or into time, subsequent analysis to allocation choices. The Unified Modeling Language (UML) is a general purpose language that does not fit to such activities. That is why the OMG has standardized a UML profile dedictated to design and analysis of Real-Time Embedded Systems (MARTE). Associated to such language, on of the goal of this thesis is to propose a clear methodology that make benefits of both MBE and Electronic System Level (ESL) techniques. Beneath the simple proposition of an MBE/ESL methodology, another goal of this thesis is to propose a better capitalization of methodology rules allowing a continuous maturity of processes. That is why we found relevant to propose an extension to SPEM in order to introduce missing concepts to acheive our goals.

The area of fault-handling in reconfigurable logic devices is one that continues to receive research attention in the field of engineering. Field Programmable Gate Arrays (FPGAs) are reconfigurable logic devices that have become an essential element in electronic hardware used for space applications, for instance deep space satellites. When electronic devices such as FPGAs are launched into space, they are relentlessly exposed to fault-inducing hazards such as high levels of radiation and extreme temperatures. The ability of the device to maintain and correct its functionality while experiencing these harsh conditions is vital to a successful mission by today's technological standards. Many techniques have been proposed for the purpose of detecting and repairing hardware faults that occur in reconfigurable logic devices. The implementation of a Genetic Algorithm (GA) as the means of repairing a faulty component has become a popular method among such techniques. A great deal of success has been demonstrated by the use of GAs in fault-repair, but there is room for improvement in the completeness of a given repair. This thesis addresses this issue by exploring the possible outcomes of implementing a voting system to work in parallel with a particular GA. Throughout the first two chapters, a general overview ofFPGAs and faulthandling techniques is provided. The advantages and disadvantages of each technique are mentioned to help re-emphasize the main purpose for the research being conducted. Once a solid background has been established regarding the main ideas behind this work, the thesis presents an in-depth description of the problem and the experimental approach that is taken. The work involves experiments which are run using a simulated FPGA that is coded in C++. A genetic algorithm is included in the program in order to simulate the repair process. By varying the parameters of the GA, as well as experimenting with the addition of a voting scheme to enhance the performance, meaningful results are discovered and presented. Fault-handling techniques proposed in the future will have a better idea of whether or not it would be beneficial to include a voting scheme to improve success.

There are many types of power sources that are used for many different applications. In this thesis, a programmable source is designed, built and tested. The programmable source is able to generate three-phase output signals from three different input voltage signals using the ADMC401 DSP board. The programmable source is unique in that it can reproduce any input signal and amplify the input signal. This is done by pulse-width modulation (PWM). The programmable source was designed with gate driver circuits, a motor controller, switches, filters, comparators and other electronic components. Thermal protection and applications for this programmable source are presented in this thesis. Also, test data taken when a squirrel cage induction motor was powered by the programmable source is presented.