Orientador: Edevar Luvizotto Júnior / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Civil, Arquitetura e Urbanismo / Made available in DSpace on 2018-08-22T20:58:38Z (GMT). No. of bitstreams: 1 Ghidetti_AriltonJose_M.pdf: 3270647 bytes, checksum: d5b718b43ee9a69efab843d850099b49 (MD5) Previous issue date: 2013 / Resumo: Este trabalho apresenta uma avaliação do emprego do Método das Vazões Mínimas Noturnas quando aplicado a um Setor de Abastecimento utilizando bombeamento direto com variação de rotação. O método de simples concepção é empregado na obtenção das informações para a elaboração de um diagnóstico de perdas de água em sistemas de abastecimento. No caso apresentado nesse trabalho o método foi aperfeiçoado possibilitando sua aplicação prática à realidade do setor investigado. Os resultados obtidos permitiram concluir que o método, após o aperfeiçoamento proposto é adequado se utilizarmos como diretriz a comparação e verificação dos resultados obtidos durante a pesquisa com o valor de perdas totais obtidos via balanço hídrico de todo o Município de Itapetininga, podendo inclusive ser utilizado em outros setores que empregam bombeamento com rotação variável, uma tendência observável nos grandes sistemas de abastecimento e, certamente para os quais o método da vazão mínima noturna pode proporcionar um efetivo suporte nas investigações de perdas / Abstract: This paper presents a review of the use of Method of Minimum Flows Night when applied to a Sector Supply using direct pumping with variable speed. The simple design method is employed to obtain the information for making a diagnosis of loss of water supply systems. In the case presented in this work the method was perfected allowing its practical application to the reality of the sector investigated. The results showed that the method after the improvement proposed is appropriate if we use as a guideline the comparison and verification of results obtained during the survey of the value of total losses obtained via water balance of the entire city of Itapetininga, and may even be used in other industries that employ variable speed pumping, a trend observable in large supply system sand certainly for which the minimum night flow method can provide an effective support in investigations of losses / Mestrado / Saneamento e Ambiente / Mestre em Engenharia Civil

Les systèmes de communications sans fil n'ont cessé d'évoluer ces dernières années, poussés par de fortes demandes du marché en systèmes toujours plus autonomes et performants. Ainsi, de nouvelles contraintes de conception sont apparues de manière à mieux prendre en compte les aspects énergétiques et ainsi améliorer la durée de vie des batteries et des circuits. Actuellement, les systèmes de communications numériques sans fil consomment d'importantes quantités d'énergie. D'autre part, la complexité des systèmes croît de génération en génération afin de satisfaire toujours plus d'utilisateurs avec un haut niveau de performances. Dans ce contexte à fortes contraintes, les circuits de type FPGA apparaissent comme une technologie attractive, pouvant supporter des circuits numériques complexes grâce à leur grand nombre de ressources. Pour pouvoir concevoir les futurs systèmes de communications numériques sans fil sur ce type de circuit, les concepteurs de tels systèmes doivent pouvoir estimer la consommation et les performances au plus tôt dans la phase de conception. De cette façon, ils pourront explorer l'espace de conception et effectuer des choix d'implémentation afin d'optimiser leurs systèmes. Durant cette thèse, une méthodologie a été proposée dont les objectifs sont d'estimer rapidement et à haut niveau la consommation de leurs circuits implantés sur FPGA ainsi que leurs performances, d'explorer l'espace de conception, de comparer efficacement plusieurs systèmes entre eux, tout en assurant une bonne précision de l'estimation. La méthodologie repose sur une phase de caractérisation de composants IP matériels ainsi que de leur modélisation en Systeme. Dans un second temps, une représentation haut-niveau du système entier est réalisée à partir de la librairie des modèles Systeme de chaque IP. A travers des simulations haut-niveau, les utilisateurs peuvent tester rapidement de multiples configurations de leur système. Un des caractères innovants de l'approche repose sur l'utilisation de signaux clés qui permettent de tenir compte des comportements dynamiques des composants IP, c-à-d leur temps d'activité (actif/inactif), au sein du système et ainsi obtenir des estimations précises. Les nombreux gains de la méthodologie ont été démontrés à travers plusieurs exemples de systèmes de communications numériques sans fil comme une chaîne de traitement en bande de base de type SISO-OFDM générique, des émetteurs LTE etc. Pour conclure, les limitations ont été adressées et des solutions d'optimisation ont pu être envisagées puis mises en place. / Wireless communication systems are still evolving since the last decades, driven by the growing demand of the electronic market for energy efficient and high performance devices. Thereby, new design constraints have appeared that aim at taking into account power consumption in order to improve battery-life of circuits. Current wireless communication systems commonly dissipate a lot of power. On the other hand, the complexity of such systems keeps on increasing through the generations to always satisfy more users at a high degree of performance. In this highly constrained context, FPGA devices seem to be an attractive technology, able to support complex systems thanks to their important number of resources. According to the FPGA nature, designers need to estimate the power consumption and the performance of their wireless communication systems as soon as possible in the design flow. In this way, they will be able to perform efficient design space exploration and make decisive implementation and optimization choices. Throughout this thesis, a power estimation methodology for hardware-focused FPGA device is described and aims at making design space exploration a lot easier, providing early and fast power and performance estimation at high-level. It also proposes an efficient way to efficiently compare several systems. The methodology is effective through an lP characterisation step and the development of their SystemC models. Then, a high level description of the entire system is realized from the SystemC models that have been previously developed. High-level simulations enable to check the functionality and evaluate the power and performance of the system. One of the contributions consists in monitoring the JP time-activities during the simulation. We show that this has an important impact on both power and performances. The effectiveness of the methodology has been demonstrated throughout several baseband processing chains of the wireless communication domain such as a SISO-OFDM generic chain, LTE transmitters etc. To conclude, the main limitations of the proposed methodology have been investigated and addressed.

Prof. A.L. Nel

Dos nos jours, l'évolution croissante des domaines d'application des circuits intégrés impose aux industriels de nouvelles contraintes de conception. Afin de réaliser des circuits électroniques plus denses et plus performants, ils cherchent à faire cohabiter plusieurs types de composants sur des surfaces plus petites et de surcroît, fonctionnant à des fréquences de plus en plus élevées. Cependant, cette cohabitation pourrait générer des problèmes de CEM (compatibilité électromagnétique). Les travaux présentés dans ce mémoire rentrent dans le cadre du projet de recherche SEISME (Simulation de l'Emission et de l'Immunité des Systèmes et Modules Electroniques). Ils décrivent des méthodologies de mesure et de modélisation de’immunité conduite des circuits intégrés complexes comme les mémoires non volatiles ou bien les microcontrôleurs. L'objectif est d'étudier l'influence des changements de composants et de cartes sur le comportement électromagnétique d'un système électronique. Dans cette perspective, afin de valider son utilisation dans le cas des circuits intégrés complexes, une étude détaillée du standard de mesure DPI (Direct Power injection) est d'abord proposée. Basé sur cette dernière, un nouveau prototype de chemin de couplage est réalisé. Ce multiplexeur permet de superposer un signal agresseur à un signal fonctionnel, avec un chevauchement de leurs bandes de fréquences. Ainsi, il est possible d'agresser une broche fonctionnelle (horloge par exemple) d'un circuit intégré pendant son fonctionnement. Ensuite, une procédure de mesure globale d'immunité conduite est présentée. Elle permet de caractériser la susceptibilité conduite des circuits complexes en tenant compte des différents modes de fonctionnement et avec la possibilité d’utiliser un critère d’immunité fonctionnel ou électrique. Grâce à l'application de cette procédure à deux mémoires non volatiles compatibles broche à broche (mêmes caractéristiques mais de deux différents fournisseurs), il est possible de constater l’influence des technologies de fabrication sur l’immunité conduite de ce type de circuits. Par conséquent, l’effet du changement de composant sur le comportement électromagnétique d’un système électronique devient prédictible. Enfin pour la modélisation, deux méthodologies sont proposées. Une au niveau composant et l'autre au niveau carte. La démarche de modélisation au niveau composant repose sur le standard ICIM-CI (Integrated Circuit Immunity Model-Conducted Immunity) et vise à générer un modèle d’immunité simulable et prédictif. Grâce à l'application de cette démarche dans le contexte des mémoires non volatiles, il est possible de prédire leur immunité dans le cas de modification de l’impédance d'entrée par rajout d'éléments de filtrage par exemple. En ce qui concerne la modélisation au niveau carte, une procédure basée sur la proposition de modèle EBIM-CI (Electronic Board Immunity Model-Conducted Immunity) est développée. Elle consiste à générer un modèle d’immunité d’une carte électronique en utilisant les modèles des différents composants qui la constituent. Un cas d’étude a été défini. Le modèle issu de cette approche permet de simuler l’immunité conduite globale du démonstrateur ainsi que de prédire le comportement électromagnétique de ce dernier lors du changement d’un ou plusieurs composants. / Nowadays, the growing evolution of application fields for integrated circuits sets new constraints for designers and manufacturers. Due to continuous technological advances in integrated circuits, those have become smaller, denser and operational at higher frequencies. The miniaturization of integrated circuits has led to the reduction of power consumption and, thus, noise margins. Mixing digital and analog functions inside the same chip also makes electromagnetic interferences (EMis) more likely to spread and cause disturbances. As a result, complex ICs with coexisting different functions represent a challenge from an EMC point of view, as interferences can cause critical functional failures. The work presented in this manuscript falls within the SEISME project which aims, among others, to perform the simulation of both the emission and the immunity of electronic systems and modules at different levels (JC, PCB, equipment, system). More precisely, this work deals with the development of measurement and modeling methodologies for the characterization of the conducted immunity of complex ICs, such as microcontrollers and non-volatile memories. The main goal is to study the effect of component and/or board replacement on the electromagnetic behavior of a complete electronic system. In this context, a thorough study of the Direct Power Injection (DPI) technique is presented, thus validating its use for complex integrated circuits. Based on this study, a new prototype for the disturbance coupling path is proposed. It consists of a multiplexer that enables the superposition of a disturbance signal and a functional one with overlapping frequency bands. Therefore, it is possible to disturb an IC functional pin (a clock for instance) during its operation. Moreover, measurement procedure for conducted immunity is introduced. Its advantage is to make it possible to characterize the immunity of complex ICs by taking into account different operation modes as well as flexible immunity criteria (electrical / functional). Thanks to the application of this methodology for two different, non-volatile, pin-to-pin-compatible memories (having the same characteristics but different manufacturers), the influence of fabrication technology on the conducted immunity of such ICs is better identified and understood. As a consequence, the effect of changing components on the electromagnetic behavior of an electronic system has become predictable. As far as modeling aspects are concerned, two methodologies are presented in this manuscript. The first one deals with the immunity at the component level whereas the other involves board level immunity. At the IC level, the modeling approach is rather based on the ICIM-CI (lntegrated Circuit Immunity Model-Conducted Immunity) draft standard which makes it possible to extract simulation models that can be incorporated within IC design flows. Once applied to the context of non-volatile memories, this approach allows predicting their immunity in the case of modified input impedance, for example. As far as immunity modeling at the board level is concerned, the idea is to make use of ICIM-CI models corresponding to different ICs on the PCB in order to construct an Electronic Board Immunity Model for Conducted Immunity (EBIM-CI). A case study has been defined and the extracted model makes it possible to simulate the demonstrator's global conducted immunity as well as to predict its electromagnetic behavior following the replacement of one or more components.

FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.

This research investigates three solutions to overcoming portability and scalability concerns in the Evolutionary Hardware (EHW) field. Firstly, the study explores if the V-FPGA—a new, portable Virtual-Reconfigurable-Circuit architecture—is a practical and viable evolution platform. Secondly, the research looks into two possible ways of making EHW systems more scalable: by optimising the system’s genetic algorithm; and by decomposing the solution circuit into smaller, evolvable sub-circuits or modules. GA optimisation is done is by: omitting a canonical GA’s crossover operator (i.e. by using an algorithm); applying evolution constraints; and optimising the fitness function. The circuit decomposition is done in order to demonstrate modular evolution. Three two-bit multiplier circuits and two sub-circuits of a simple, but real-world control circuit are evolved. The results show that the evolved multiplier circuits, when compared to a conventional multiplier, are either equal or more efficient. All the evolved circuits improve two of the four critical paths, and all are unique. Thus, it is experimentally shown that the V-FPGA is a viable hardware-platform on which hardware evolution can be implemented; and how hardware evolution is able to synthesise novel, optimised versions of conventional circuits. By comparing the and canonical GAs, the results verify that optimised GAs can find solutions quicker, and with fewer attempts. Part of the optimisation also includes a comprehensive critical-path analysis, where the findings show that the identification of dependent critical paths is vital in enhancing a GA’s efficiency. Finally, by demonstrating the modular evolution of a finite-state machine’s control circuit, it is found that although the control circuit as a whole makes use of more than double the available hardware resources on the V-FPGA and is therefore not evolvable, the evolution of each state’s sub-circuit is possible. Thus, modular evolution is shown to be a successful tool when dealing with scalability.

This diploma thesis deals with developing of software, which allows access and control of programmable controllers through web interface. Software uses client server model and for communication between client and server is used Windows Communication Foundation interface which is integrated in Microsoft .NET Framework from version 3.0. Applications were written in C# programming language using .NET Framework libraries. Data visualization in web application was created by Microsoft Silverlight.

The diploma thesis deals with control of robotic manipulators and their range of applicability. The main objective is to create kinetic model of manipulator in the SolidWorks environment and to set up the identification and control program in the LabVIEW software. It evaluates the applicability of SoftMotion Module tool, which was developed especially for the model control in Motion analysis. The proposed method of control is used on the kinetic model, which employs control commands for the movement of manipulator MiniSwing

Main topic of this master's thesis is proposal of automatic line for bulding and testing keys for electrical ignition of cars. In the first part of this master's thesis you can see options of layout machines and proposal of two layouts. In this part you can see all actuators and senzors with detailed description of using in application, too. Next part is about software, communication between each components and description of visualization. Last part is about recapitulate of topic and evaluation building of machines with ideas for improvement this line for future.