FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture for all Xilinx 7-Series FPGAs that is scalable to large arrays. The two primary sources of overhead associated with FPGA BIST, the test time and the memory required for storing the BIST configurations, are also reduced when compared to previous FPGA-BIST approaches. The BIST techniques presented here also eliminate the need for using any of the user I/O pins, such as a clock, a reset, and test observation pins; therefore, it is suitable for immediate deployment on any system with Xilinx 7-Series FPGAs. With faults detected, isolated, and corrected, the effective MTBF of a system can be extended. / Master of Science

The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance of modern embedded processors, they are outpaced by computational demands of the growing number of modern applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and estimate the integration overhead and consequently the hardware acceleration benefit before committing to implementation. In this work, we present FPGA-Roofline, a visual model that offers insights to designers and developers to have realistic expectations of their system and that enables them to do their design and analysis in a faster and more efficient fashion. FPGA-Roofline allows simultaneous analysis of communication and computation resources in FPGA-based hardware accelerators. To demonstrate the effectiveness of our model, we have implemented hardware accelerators in FPGA and used our model to analyze and optimize the overall system performance. We show how the same methodology can be applied to the design process of any FPGA-based hardware accelerator to increase productivity and give insights to improve performance and resource utilization by finding the optimal operating point of the system. / Master of Science

The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom hardware design language and communication synthesis. The framework is designed to optimize performance with matrix-type mathematical operations. The largest matrices used in this process are 4x4 matrices. The primary example modeled in this work is MIMO decoding. Making this possible are 16 functional unit containers within the framework, with generalized interfaces, which can hold custom user hardware and IP cores. This framework, which is controlled by a microsequencer, is centered on a matrix-based memory structure comprised of 64 individual dual-ported memory blocks. The microsequencer uses an instruction word that can control every element of the architecture during a single clock cycle. Routing to and from the memory structure uses an optimized form of a crossbar switch with predefined routing paths supporting any combination of input/output pairs needed by the algorithm. A goal at the start of the design was to achieve a clock speed of over 100 MHz; a clock speed of 183 MHz has been achieved. This design is capable of performing a 4x4 matrix inversion within 335 clock cycles, or 1,829 ns. The power efficiency of the design is measured at 17.15 MFLOPS/W. / Master of Science

The modular design methodology has been widely adopted to harness the complexity of large FPGA-based systems. As a result, a number of commercial and academic tool flows emerged to support modular design including Hierarchical Design Flow and Partial Reconfiguration Flow, OpenPR, HMFlow, PARBIT, REPLICA, GoAhead and QFlow frameworks. As all of these projects have shown, a modular approach raises the abstraction level, provides clear boundaries for incremental design, reduces placement complexity, and improves productivity. At the physical layer, modules can be compiled into rectangular regions, suitable for placement on the FPGA fabric. Creating a design then becomes the process of placing all of the modules on the FPGA, followed by inter-module routing. FPGAs, however, are not homogenous, and the shape of individual modules could greatly impact overall device utilization. Prior work in modular assembly utilize modules with a single shape and aspect ratio in the assembly process. Due to the increasing size and heterogeneity of contemporary FPGAs, the placement flexibility of such a module is becoming increasingly limited. This thesis introduces a process that exploits offline shape generation and exploration, enabling the selection of shapes using criterias such as resource usage efficiency, placement flexibility, and device utilization. Module shapes can be generated with these criterias in mind while still taking advantage of the reduced placement complexity of modular design and assembly / Master of Science

A microcomputer-based process controller has been developed to produce porous membrane material. The production process is based on stretching the material in a constant temperature solvent bath. This thesis describes the hardware and software designed to direct and monitor the process. A VIC 20 is used as the process-controlling microcomputer. The system features two dedicated motor controllers and two channels for controlling temperature. The motor controllers determine the material feed rate and rate of stretch. The temperature controllers keep the system at a selectable constant temperature. An interactive assembly language program directs the entire process and monitors the controlled variables. A complete description of the interface and temperature control circuitry is given. The software used to direct the process is also discussed and presented. / Master of Science

A simulator for use in programmable controller ladder logic testing is developed. A simulation language, based on SIMSCRIPT 11.5, to model ladder logic run physical systems is also designed. This System Description Language (SDL) handles simulations of the physical systems and the corresponding ladder-system interactions via the usage of specially designed constructs. The simulation package uses as input an SDL program file describing the system to be simulated, and a ladder file containing the ladder written to control this system. The simulation processor generates the actual simulation from the description contained in the SDL program file. A ladder scanning procedure approximates the actual programmable controller scan as closely as possible. The simulator also incorporates the ability for the user to dynamically interact with, and control the simulation by manipulating ladder inputs from the keyboard. A rolling timing diagram display of a maximum of 7 elements can be created and continuously updated for viewing purposes. System simulations of functionally different manufacturing systems are created and run with their respective ladders on the simulator. Different ladders for the same system are compared for evaluating the performance of the control logic of each ladder. These comparisons are based on the viewing of timing diagrams generated by the ladders. Thus, an off-line ladder logic debugging environment is created. / Master of Science

Digital signal processing systems demand higher computational performance and more operations per second than ever before, and this trend is not expected to end any time soon. Processing architectures must adapt in order to meet these demands. The two techniques most prevalent for achieving throughput constraints are parallel processing and stream processing. By combining these techniques, significant throughput improvements have been achieved. These preliminary results apply to specific applications, and general tools for automation are in their infancy. In this dissertation techniques are developed to automatically generate efficient parallel streaming hardware architectures. / Ph. D.

Traditionally, achieving good performance for a multi-hop wireless network is known to be difficult. The main approach to control the operation of such a network relies on a distributed paradigm, assuming that a centralized approach is not feasible. Relying on a distributed paradigm could be justified at the time when the basic technical building blocks (e.g., node computational power, communication technology, positioning technology) were the bottlenecks. Recent advances and breakthroughs in these technical areas along with the emergence of programmable networks with softwarized control plane intelligence allow us to consider employing a centralized optimization paradigm to control and manage the operation of a multi-hop wireless network. The programmable control provides a platform on which the centralized global network optimization paradigm can be supported. The benefits of a centralized network optimization lie specially in that a network may be configured in such a way that offers optimal performance, which is hardly possible for a network relying on distributed operation. The objectives of this dissertation are to fully understand the potential benefits of a centralized control plane for a multi-hop wireless network, to identify any new challenges under this new paradigm, and to devise innovative solutions for optimal performance via a centralized control plane. Given that the performance of a wireless network heavily depends on its physical layer capabilities, we will consider a number of advanced wireless technologies, including MIMO, full duplex, and interference cancellation at the physical layer. The focus is on building tractable computational models for these wireless technologies that can be used for modeling, analysis and optimization in the centralized control plane. Problem formulation and efficient solution procedures are developed for various centralized optimization problems across multiple layers. End-to-end throughput maximization is a key objective among these optimization problems on the centralized control plane and is used to demonstrate the superior advantage of this paradigm. We study several problems: • Integration of SIC and MIMO DoF IC. We propose to integrate MIMO Degree-of-Freedom (DoF) interface cancellation (IC) and Successive Interference Cancellation (SIC) in MIMO multi-hop network under DoF protocol model. We show that DoF-based IC and SIC can be jointly integrated to combat the interference more effectively and improve the end-to-end throughput significantly. We develop the necessary mathematical models to realize the idea in a multi-hop wireless network. • Full-Duplex MIMO Wireless Networks Throughput. We investigate the performance of MIMO full-duplex (FD) in a multi-hop network. We show that if IC is exploited, MIMO FD can achieve significant throughput gain over MIMO HD in a multi-hop network, which is contrary to the recent literature suggesting an unexpected marginal gain. Our proposed model handles the additional network interference by joint efficient link scheduling and interference cancellation. • PCP in Tactical Wireless Networking. We propose the idea of the Programmable Control Plane (PCP) for the tactical wireless network under the protocol model. PCP decouples the control and data plane and allows the network control layer functionalities to be dynamically configured to adapt to specific wireless channel conditions, customized applications and/or certain tactical situations. The proposed PCP functionalities are cast into a centralized optimization problem, which can be updated as needed and provide a centralized intelligence to manage the operation of a wireless MIMO multi-hop network under the protocol model. • UPCP in Heterogeneous Wireless Networks. We propose the idea of the Unified Programmable Control Plane (UPCP) for tactical heterogeneous wireless networks with interference management capabilities under the SINR model. The UPCP abstracts the complexity of the underlying network comprised of heterogeneous wireless technologies and provides a centralized intelligence over the network resources. We develop necessary mathematical model to realize the UPCP. / Ph. D.

The continued expansion of the Internet of Things (IoT) in recent years has introduced a myriad of concerns about its security. There have been numerous examples of IoT devices being attacked, demonstrating the need for integrated security. The vulnerability of data transfers in the IoT can be addressed using cryptographic protocols. However, IoT devices are resource-constrained which makes it difficult for them to support existing standards. To address the need for new, standardized lightweight cryptographic algorithms, the National Institute of Standards and Technology (NIST) began a Lightweight Cryptography Standardization Process. This work analyzes the Sparkle (Schwaemm and Esch) submission to the process from a hardware based perspective. Two baseline implementations are created, along with one implementation designed to be resistant to side channel analysis and an incremental implementation included for analysis purposes. The implementations use the Hardware API for Lightweight Cryptography to facilitate an impartial evaluation. The results indicate that the side channel resistant implementation resists leaking data while consuming approximately three times the area of the unprotected, incremental implementation and experiencing a 27% decrease in throughput. This work examines how all of these implementations perform, and additionally provides analysis of how they compare to other works of a similar nature. / Master of Science / In today's society, interactions with connected, data-sharing devices have become common. For example, devices like "smart" watches, remote access home security systems, and even connected vending machines have been adopted into many people's day to day routines. The Internet of Things (IoT) is the term used to describe networks of these interconnected devices. As the number of these connected devices continues to grow, there is an increased focus on the security of the IoT. Depending on the type of IoT application, a variety of different types of data can be transmitted. One way in which these data transfers can be protected is through the use of cryptographic protocols. The use of cryptography can provide assurances during data transfers. For example, it can prevent an attacker from reading the contents of a sensitive message. There are several well studied cryptographic protocols in use today. However, many of these protocols were intended for use in more traditional computing platforms. IoT devices are typically much smaller in size than traditional computing platforms. This makes it difficult for them to support these well studied protocols. Therefore, there have been efforts to investigate and standardize new lightweight cryptographic protocols which are well suited for smaller IoT devices. This work analyzes several hardware implementations of an algorithm which was proposed as a submission to the National Institute of Standards and Technology (NIST) Lightweight Cryptography Standardization Process. The analysis focuses on metrics which can be used to evaluate its suitability for IoT devices.

Nowadays, security is one of the foremost concerns as the confidence in a system is mostly dependent on its ability to protect itself against any attack. The area of Electromagnetic Fault Injection (EMFI) wherein attackers can use electromagnetic (EM) pulses to induce faults has started garnering increasing attention. It became crucial to understand EM attacks and find the best countermeasures. In this race to find countermeasures, different researchers proposed their ideas regarding the generation of EM attacks and their detection. However, it is difficult to see a universal agreement on the nature of these attacks. In this work, we take a closer look at the analysis of the primary EMFI fault models suggested earlier. Initial studies had shown that EM glitches caused timing violations, but recently it was proposed that EM attacks can create bit sets and bit resets. We performed a detailed experimental evaluation of the existing detection schemes on two different FPGA platforms. We present their comparative design analysis concerning their accuracy, precision, and cost. We propose an in situ timing sensor to overcome the disadvantages of the previously proposed detection approaches. This sensor can successfully detect most of the electromagnetic injected faults with high precision. We observed that the EM attack behaves like a localized timing attack in FPGAs which can be identified using the in situ timing sensors. / MS / When computers are built only for a specific application, they are called embedded systems. Over the past decade, there has been an incredible increase in the number of embedded systems around us. Right from washing machines to electronic locks, we can see embedded systems in almost every aspect of our lives. There is an increasing integration of embedded systems in applications such as cars and buildings with the advent of smart technologies. Due to our heavy reliance on such devices, it is vital to protect them against intentional attacks. Apart from the software attacks, it is possible for an attacker to disrupt or control the functioning of a system by physically attacking its hardware using various techniques. We look at one such technique that uses electromagnetic pulses to create faults in a system. We experimentally evaluate two of the previously suggested methods to detect electromagnetic injection attacks. We present a new sensor for this detection which we believe is more effective than the previously discussed detection schemes.