<p>Most of today’s microwave circuits are designed for specific function and specialneed. There is a growing trend to have flexible and reconfigurable circuits. Circuitsthat can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured toachieve the desired performance seems to be challenging. However, with recentadvances in many areas of technology these demands can now be met.</p><p>Two concepts have been investigated in this thesis. The initial part presents thefeasibility of a flexible and programmable circuit (PROMFA) that can be utilized formultifunctional systems operating at microwave frequencies. Design details andPROMFA implementation is presented. This concept is based on an array of genericcells, which consists of a matrix of analog building blocks that can be dynamicallyreconfigured. Either each matrix element can be programmed independently or severalelements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters oroscillators. Realization of a flexible RF circuit based on generic cells is a new concept.In order to validate the idea, a test chip has been fabricated in a 0.2μm GaAs process, ED02AH from OMMIC^TM. Simulated and measured results are presented along withsome key applications like implementation of a widely tunable band pass filter and anactive corporate feed network.</p><p>The later part of the thesis covers the design and implementation of tunable andwideband highly linear LNAs that can be very useful for multistandard terminals suchas software defined radio (SDR). One of the key components in the design of a flexibleradio is low noise amplifier (LNA). Considering a multimode and multiband radiofront end, the LNA must provide adequate performance within a large frequency band.Optimization of LNA performance for a single frequency band is not suitable for thisapplication. There are two possible solutions for multiband and multimode radio frontends (a) Narrowband tunable LNAs (b) Wideband highly linear LNAs. A dual bandtunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuningtechnique has also been proposed for the optimization of this LNA. This thesis alsopresents the design of a novel highly linear current mode LNA that can be used forwideband RF front ends for multistandard applications. Technology process for thiscircuit is 90nm CMOS.</p>

Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping of general-purpose graphics processing units (GPGPUs) on field programmable gate arrays (FPGAs) using a novel tool chain. This hardware flow combined with the higher level simulation flow using the same source code allowed us to create a whole tool chain to study and build future architectures using new technologies. It also gave us enough flexibility at different granularities to make architectural decisions. We will also discuss some example systems that were built using this tool chain along with some results.

Zugl.: Bochum, Univ., Diss., 2009

Les convertisseurs de puissance en DC/DC sont largement utilisés pour les applications domestiques et industrielles pour des puissances de quelques Watts à quelques MégaWatts. Généralement, pour chaque application un convertisseur adapté est conçu afin de répondre au cahier des charges. A chaque nouvelle application correspond donc un nouveau convertisseur, ce qui conduit à concevoir systématiquement de nouvelles structures de conversion et qui s'avère coûteux en temps et en argent. Eventuellement, cela peut conduire à des développements technologiques spécifiques qui, eux aussi ont des conséquences sur le coût de développement des solutions d'électronique de puissance.Afin de contourner ces difficultés, mes travaux de thèse portent sur la démarche Réseaux de Micro Convertisseurs (RµC) qui propose une nouvelle approche permettant de répondre de manière totalement flexible à n’importe quel cahier des charges. Cette approche vise à créer un composant unique, appelé cellule élémentaire (CE), permettant de répondre à tout type de cahiers des charges par la mise en série et/ou en parallèle de plusieurs de ces cellules élémentaires. Elle permet ainsi de régler les calibres en tension et/ou en courant du convertisseur à réaliser. Mes travaux de thèse se divisent en deux grandes parties. La première partie consiste en la conception et l’intégration de la cellule élémentaire utilisée dans le RµC. La deuxième, aborde les stratégies de configuration utilisées dans les RµC ainsi que les modes d’association des cellules élémentaires pouvant répondre à n’importe quel cahier des charges. / DC/DC power converters are widely used for domestic and industrial applications with powers from a few watts to several MegaWatts. Generally, for each application, an appropriate converter is designed to meet the specifications. So, with a new application corresponds a new converter leading to systematic review and re-design of a new structure of conversion which is costly in time and money. Eventually, it can lead to specific technological developments which also have an impact on the cost of developing solutions for power electronics. To circumvent these difficulties, my thesis focuses on the process of Micro Converters Networks (MiCoNet) which proposes a new approach to respond fully flexibely to any specifications. The aim of this approach is to create a unit component, called elementary cell, able to respond to any kind of specifications by connecting in series and/or parallel several of these elementary cells. It permits to adjust the voltage and/or current of the converter to achieve. Therefore, my thesis is divided into two main parts. The first part consists in the design and the integration of the elementary cell used in the MiCoNet. The second discusses the configuration strategies used in the MiCoNet and association modes of elementary cells which can respond to any specification.

Que ce soit au travers des smartphones, des consoles de jeux portables ou bientôt des supercalculateurs, les systèmes sur puce (System-on-chip (SoC)) ont vu leur utilisation largement se répandre durant ces deux dernières décennies. Ce phénomène s’explique notamment par leur faible consommation de puissance au regard des performances qu’ils sont capables de délivrer, et du large panel de fonctions qu’ils peuvent intégrer. Les SoC s’améliorant de jour en jour, ils requièrent de la part des systèmes d’interconnexions qui supportent leurs communications, des performances de plus en plus élevées. Pour répondre à cette problématique les réseaux sur puce (Network-on-Chip (NoC)) ont fait leur apparition.En plus des ASIC, les circuit reconfigurables FPGA sont un des choix possibles lors de la réalisation d’un SoC. Notre première contribution a donc été de réaliser et d’étudier les performances du portage du réseau sur puce générique Hermes initialement conçu pour ASIC, sur circuit reconfigurable. Cela nous a permis de confirmer que l’architecture du système d’interconnexions doit être adaptée à celle du circuit pour pouvoir atteindre les meilleures performances possibles. Par conséquent, notre deuxième contribution a été la conception de l’architecture de TrustNoC, un réseau sur puce optimisé pour FPGA à hautes performances en latence, en fréquence de fonctionnement, et en quantité de ressources logiques occupées.Un autre aspect primordial qui concerne les systèmes sur puce, et plus généralement de tous les systèmes numériques est la sécurité. Notre dernière principale contribution a été d’étudier les menaces qui s’exercent sur les SoC durant toutes les phases de leur vie, puis de développer à partir d’un modèle de menaces, des mécanismes matériels de sécurité permettant de lutter contre des détournements d’IP, et des attaques logicielles. Nous avons également veillé à limiter au maximum le surcoût qu’engendre les mécanismes de sécurité sur les performances sur réseau sur puce. / Whether through smartphones, portable game consoles, or high performances computing, Systems-on-Chip (SoC) have seen their use widely spread over the last two decades. This can be explained by the low power consumption of these circuits with the regard of the performances they are able to deliver, and the numerous function they can integrate. Since SoC are improving every day, they require better performances from interconnects that support their communications. In order to address this issue Network-on-Chip have emerged.In addition to ASICs, FPGA circuits are one of the possible choices when conceiving a SoC. Our first contribution was therefore to perform and study the performance of Hermes NoC initially designed for ASIC, on reconfigurable circuit. This allowed us to confirm that the architecture of the interconnection system must be adapted to that of the circuit in order to achieve the best possible performances. Thus, our second contribution was to design TrustNoC, an optimized NoC for FPGA platform, with low latency, high operating frequency, and a moderate quantity of logical resources required for implementation.Security is also a primordial aspect of systems-on-chip, and more generally, of all digital systems. Our latest contribution was to study the threats that target SoCs during all their life cycle, then to develop and integrate hardware security mechanisms to TrustNoC in order to counter IP hijacking, and software attacks. During the design of security mechanisms, we tried to limit as much as possible the overhead on NoC performances.

Neste trabalho de pesquisa, foi realizado um estudo dos principais tipos de ferramentas para modelagem de hardware buscando-se verificar as vantagens da utilização de Redes de Petri para a modelagem de sistemas dinâmicos e concorrentes e de sua implementação em hardware. Observou-se que apesar de existirem ferramentas para esta finalidade, existem pontos que podem ser trabalhados para facilitar o acesso a esta tecnologia. Assim, foi desenvolvido um método para facilitar a implementação de sistemas modelados em Redes de Petri, em hardware de lógica reconfigurável. Para isto, utilizou-se um software de captura onde, a partir do gráfico do modelo em Rede de Petri, é gerado um arquivo de descrição no formato PNML - Linguagem de Marcação para Rede de Petri (Petri Net Markup Language). A partir desta descrição, é gerado um arquivo de descrição de hardware no formato VHDL - Linguagem de Descrição de Hardware VHSIC (VHSIC Hardware Description Language), que pode ser gravado em um circuito de lógica reconfigurável. Para possibilitar esta etapa, foi realizado o desenvolvimento de uma ferramenta que gera um arquivo em linguagem VHDL a partir da descrição no formato PNML. A ferramenta desenvolvida é descrita em detalhes, mostrando todas as etapas e critérios utilizados na conversão. Para validar o método, é mostrado um exemplo de aplicação com a implementação em FPGA - Matriz de Portas Programável em Campo (Field Programmable Gate Arrow), de uma Rede de Petri modelando uma planta industrial hipotética. Finalmente é feita uma comparação de desempenho entre o modelo executado em hardware com o modelo executado em software. / In this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally, a performance comparison is made between the model executed in hardware and the model executed in software.

Neste trabalho de pesquisa, foi realizado um estudo dos principais tipos de ferramentas para modelagem de hardware buscando-se verificar as vantagens da utilização de Redes de Petri para a modelagem de sistemas dinâmicos e concorrentes e de sua implementação em hardware. Observou-se que apesar de existirem ferramentas para esta finalidade, existem pontos que podem ser trabalhados para facilitar o acesso a esta tecnologia. Assim, foi desenvolvido um método para facilitar a implementação de sistemas modelados em Redes de Petri, em hardware de lógica reconfigurável. Para isto, utilizou-se um software de captura onde, a partir do gráfico do modelo em Rede de Petri, é gerado um arquivo de descrição no formato PNML - Linguagem de Marcação para Rede de Petri (Petri Net Markup Language). A partir desta descrição, é gerado um arquivo de descrição de hardware no formato VHDL - Linguagem de Descrição de Hardware VHSIC (VHSIC Hardware Description Language), que pode ser gravado em um circuito de lógica reconfigurável. Para possibilitar esta etapa, foi realizado o desenvolvimento de uma ferramenta que gera um arquivo em linguagem VHDL a partir da descrição no formato PNML. A ferramenta desenvolvida é descrita em detalhes, mostrando todas as etapas e critérios utilizados na conversão. Para validar o método, é mostrado um exemplo de aplicação com a implementação em FPGA - Matriz de Portas Programável em Campo (Field Programmable Gate Arrow), de uma Rede de Petri modelando uma planta industrial hipotética. Finalmente é feita uma comparação de desempenho entre o modelo executado em hardware com o modelo executado em software. / In this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally, a performance comparison is made between the model executed in hardware and the model executed in software.

Orientadores: Guido Costa Souza de Araujo, Alexandre Xavier Falcão / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-07T09:45:52Z (GMT). No. of bitstreams: 1 Cappabianco_FabioAugustoMenocci_M.pdf: 2472578 bytes, checksum: 8df546b29eccff4337413df4b5d9a7c3 (MD5) Previous issue date: 2006 / Resumo: Implementações de operadores de processamento de imagens em plataformas de hardware têm obtido ótimos resultados devido a sua atuação paralela em diversas regiões da imagem. Ao mesmo tempo, a IFT (Image Foresting Transform) tem provado ser uma técnica eficiente de reduzir problemas de processamento de imagens em um problema de floresta de caminhos de um grafo, cuja solução é obtida em tempo linear no o número de pixels. Este trabalho contém a implementação de uma plataforma, em hardware, chamada SIFT {Silicon Image Foresting Transform), que executa o algoritmo da IFT paralelamente. O modelo de processamento e armazenamento SIFT serve como base para outras arquiteturas de processamento de imagens e amplia o entendimento de alguns conceitos de mapas de predecessores e rótulos utilizados pela IFT. / Abstract: Great results had been achieved by the use of hardware platforms to implement image processing operators. This success was reached due to the use of multiple processors working parallel in several regions of the image. On the other hand, IFT (Image Foresting Transform), a software technique to reduce image processing problems into a graph path forest problem, performs image operations in linear time in the number of pixels in most of applications. The main goal of this work was to generate a hardware platform, that implements the an algorithm based on the IFT in a fast and efficient way. / Mestrado / Mestre em Ciência da Computação

Orientadores: Dalton Soares Arantes, Fabbryccio A. Cardoso / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-08T03:13:26Z (GMT). No. of bitstreams: 1 Garcia_FabioLumertz_M.pdf: 3287022 bytes, checksum: 7cf0e283ddc5a0d2f929f3cc22b17903 (MD5) Previous issue date: 2006 / Resumo: O objetivo deste trabalho é apresentar as diversas etapas de implementação de um codificador LDPC para um sistema de televisão digital, desenvolvido através do emprego de algumas tecnologias inovadoras de prototipagem rápida em FPGA. O codificador implementado foi baseado em um código LDPC eIRA, que consiste em uma classe estendida de códigos de repetição e acumulação irregulares, com palavra-código de 9792 bits e taxa de 3/4. Visando agregar outras tecnologias emergentes ao projeto de TV Digital, o sistema proposto foi desenvolvido para operar sobre o Protocolo de Internet - IP. Os esforços para a realização deste trabalho fizeram parte de um esforço mais amplo de um consórcio de universidades brasileiras, visando à concepção, ao projeto, à simulação e à implementação em hardware de um Sistema de Modulação Inovadora para o SBTVD. A grande sinergia obtida neste projeto e o uso intensivo de ferramentas de prototipagem rápida em FPGA possibilitaram a obtenção de uma prova de conceito implementada e testada em um prazo de apenas 12 meses / Abstract: This work presents the several phases in the implementation of an LDPC encoder for a digital television system, developed using innovative technologies for rapid prototyping on Field Programmable Gate Array devices - FPGAs. The implemented encoder was based on an eIRA - extended Irregular Repeat Accumulate - LDPC code with codeword-Iength equal to 9792 bits and rate 3/4. The proposed system was developed to work with video streaming over the Internet Protocol- IP. This work is part of a more ambitious project that resulted in the development of an advanced Modulation System for the Brazilian Digital TV System - BTVD / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

Les travaux présentés dans ce mémoire de thèse s'intéressent à la génération et à la mise en œuvre de séquences de test pour le test de conformité de contrôleurs logiques. Dans le cadre de ces travaux, le Grafcet (IEC 60848 (2002)), langage de spécification graphique utilisé dans un contexte industriel, a été retenu comme modèle de spécification. Les contrôleurs logiques principalement considérés dans ces travaux sont les automates programmables industriels (API). Afin de valider la mise en œuvre du test de conformité pour des systèmes de contrôle/commande critiques, les travaux présentés proposent: - Une formalisation du langage de spécification Grafcet. En effet, l'application des méthodes usuelles de vérification et de validation nécessitent la connaissance du comportement à partir de modèles formels. Cependant, dans un contexte industriel, les modèles utilisés pour la description des spécifications fonctionnelles sont choisis en fonction de leur pouvoir d'expression et de leur facilité d'utilisation, mais ne disposent que rarement d'une sémantique formelle. - Une étude de la mise en œuvre de séquences de test et l'analyse des verdicts obtenus lors du changement simultané de plusieurs entrées logiques. Une campagne d'expérimentation a permis de quantifier, pour différentes configurations de l'implantation, le taux de verdicts erronés dus à ces changements simultanés. - Une définition du critère de SIC-testabilité d'une implantation. Ce critère, déterminé à partir de la spécification Grafcet, définit l'aptitude d'une implantation à être testée sans erreur de verdict. La génération automatique de séquences de test minimisant le risque de verdict erroné est ensuite étudiée. / The works presented in this PhD thesis deal with the generation and implementation of test sequences for conformance test of logic controllers. Within these works, Grafcet (IEC 60848 (2002)), graphical specification language used in industry, has been selected as the specification model. Logic controllers mainly considered in these works are Programmable Logic Controllers (PLC). In order to validate the carrying out of conformance test of critical control systems, this thesis presents: - A formalization of the Grafcet specification language. Indeed, to apply usual verification and validation methods, the behavior is required to be expressed through formal models. However, in industry, the models used to describe functional specifications are chosen for their expression power and usability, but these models rarely have a formal semantics. - A study of test sequences execution and analysis of obtained verdicts when several logical inputs are changed simultaneously. Series of experimentation have permitted to quantify, for different configurations of the implantation under test, the rate of erroneous verdicts due to these simultaneous changes. - A definition of the SIC-testability criterion for an implantation. This criterion, determined on the Grafect specification defines the ability of an implementation to be tested without any erroneous verdict. Automatic generation of test sequences that minimize the risk of erroneous verdict is then studied.