Background. Automation in production has become a necessity for producing companies to keep up with the demand created by their customers. One way to automate a process is to use a piece of hardware called a programmable logic controller (PLC). A PLC is a small computer capable of being programmed to process a set of inputs, from e.g. sensors, and create outputs, to e.g. actuators, from that. This eliminates the risk of human errors while at the same time speeding up the production rate of the now near identical products. To improve the automation process on the shop floor and the production process in general a special software system is used. This system is known as the manufacturing execution system (MES), and it is connected to the PLCs and other devices on the shop floor. The MES have different functionalities and one of these is that it can manage instructions. Theses instructions can be aimed to both employees and devices such as the PLCs. Would the MES suffer from an error, e.g. in the instructions sent to the shop floor, the company could suffer from a negative impact both economical and in reputation. Since the PLC is a computer and it is connected to the MES it might be possible to attack the system using the PLC as leverage. Objectives. Examine if it is possible to attack the MES using a PLC as the attack origin. Methods. A literature study was performed to see what types of attacks and vulnerabilities that has been disclosed related to PLCs between 2010 and 2018. Secondly a practical experiment was done, trying to perform attacks targeting the MES. Results. The results are that there are many different types of attacks and vulnerabilities that has been found related to PLCs and the attacks done in the practical experiment failed to induce negative effects in the MES used. Conclusions. The conclusion of the thesis is that two identified PLC attack techniques seems likely to be used to attack the MES layer. The methodology that was used to attack the MES layer in the practical experiment failed to affect the MES in a negative way. However, it was possible to affect the log file of the MES in one of the test cases. So, it does not rule out that other MES types are not vulnerable or that the two PLC attacks identified will not work to affect the MES. / Bakgrund. Automatisering inom produktion har blivit nödvändigt för att företag ska kunna tillgodose den efterfrågan som deras kunder skapar. Ett sätt att automatisera denna process är genom att använde en typ av hårdvara som på engelska kallas för programmable logic controller (PLC). En PLC är en liten dator som man kan programmera så att den bearbetar signaler in, från t.ex. sensorer, och skapar signaler ut, till t.ex. motorer, från det. Detta eliminerar då risken för mänskliga fel samtidigt som det snabbar upp produktionen av de nu nästan identiska produkterna. För att förbättra automatiseringsprocessen på golvet i fabrikerna och även tillverkningsprocessen generellt så används ett speciellt mjukvarusystem. Detta system kallas på engelska execution manufacturing system (MES), och detta system är kopplat till PLCerna och annan utrustning på produktionsgolvet. MESen har olika funktionaliteter och en utav dessa är hantering av instruktioner. Dessa instruktioner kan vara riktade både till anställda samt utrustning så som PLCer. Skulle det inträffa ett fel i MESen, t.ex. i instruktionerna som skickas till produktionsgolvet, så skulle företaget kunna få lida av negativa konsekvenser både ekonomiskt och för företagets rykte. I och med att en PLC är en dator och den är kopplad till MES så kan det finnas möjligheter att utföra attacker mot MESen genom att använda en PLC som utgångspunkt. Syfte. Undersöka om det är möjligt att utföra en attack på en MES med utgångspunkt från en PLC. Metod. En litteraturstudie genomfördes för att ta reda på vilka typer av attacker samt sårbarheter relaterade till PLCer som publicerats mellan 2010 och 2018. Ett praktiskt experiment utfördes också, där attackförsök gjordes på ett MES. Resultat. Resultatet är att det finns många olika attacktyper samt sårbarheter som upptäckts relaterade till PLCer och att de attacker som utfördes i det praktiska experimentet inte lyckades skapa några negativa effekter i det MES som användes. Slutsatser. Slutsatsen för examensarbetet är att två olika typer av de hittade PLC-attackerna verkar vara kapabla till att användas för att attackera MES-lagret. Metoden som användes i det praktiska försöket lyckades inte påverka MES-lagret negativt. Men det gick att påverka MESens logfil i ett av testfallen, så det går inte att fastslå att andra MES-typer inte är sårbara mot detta eller att de två identifierade PLC-attackerna inte kommer kunna påverka MES-lagret negativt.

Reconfigurable circuits (Field Programmable Gate Arrays (FPGAs)) for accelerating applications have been a key technology for many years. Thus, the world’s leading data center operators and providers of cloud infrastructures, namely Microsoft, IBM, and soon Amazon, are using FPGAs on their application platforms. The central question of this contribution is how FPGAs can be virtualized for a flexible and dynamic deployment in cloud infrastructures. In addition to the virtualization of FPGA resources, service models for the provision of virtualized FPGAs are developed and embedded into a resource management system in order to evaluate the cloud system’s behaviour. The objective of this work is not to build a cloud architecture, but rather to examine selected aspects of cloud systems with regard to the integration of reconfigurable hardware. The FPGAs are not only virtualized but, unlike in many other projects, the entire system and the application are taken into account. As a result, the vFPGAs are used dynamically and adaptively at different locations and topologies in the cloud architecture, depending on the user’s requirements. Furthermore, a prototypical implementation of a cloud system has been developed, and evaluated in several projects. The virtualization using state-of-the-art FPGAs has shown that the establishment of homogenous environments is possible. The Migration of a partial FPGA context is also possible with current FPGA architectures, but is associated with high costs in form of hardware resources. Furthermore, a simulation was carried out to determine whether virtualization and migration, could contribute to a more efficient utilization of resources in a larger cloud system or impair the service level agreement. In summary, both the developed virtualization and the possibility of a migration make it possible to reduce the amount of necessary resources in a modern cloud system. / Rekonfigurierbare Schaltkreise wie Field Programmable Gate Arrays (FPGAs) stellen seit Jahren für viele Unternehmen eine Schlüsseltechnologie zur Hintergrundbeschleunigung von Anwendungen und Cloud- Diensten dar. Als weltweit führende Betreiber von Rechenzentren und Anbieter von Cloud-Infrastrukturen setzten mittlerweile Microsoft, IBM und demnächst auch Amazon in ihren Systemen FPGAs auf Anwendungsebene ein, um sowohl die Rechenleistung zu erhöhen als auch die Verlustleistung und damit die Betriebskosten zu reduzieren. Ebenso stellt die Erhöhung der Zugangssicherheit durch Nutzung von FPGAs einen weiteren bedeutenden Aspekt dar. Die zentrale Fragestellung dieser Arbeit besteht darin, wie FPGAs durch Virtualisierung effizient auf der Anwendungsebene nutzbar gemacht werden können. Das Ziel besteht darin, die FPGAs wie andere Komponenten flexibel und dynamisch in der Cloud einzusetzen. Um ein Cloud-System mit FPGAs evaluieren zu können, werden zunächst Servicemodelle für eine Bereitstellung der virtualisierten FPGAs entwickelt und in eine Ressourcenverwaltung eingebettet. Ziel der Arbeit ist hierbei nicht der Aufbau einer Cloud-Architektur selbst, sondern vielmehr die Untersuchung ausgewählter Aspekte mit Hinblick auf die Integration rekonfigurierbarer Hardware in eine Cloud. Dabei wird die klassische System-Virtualisierung auf die rekonfigurierbare Hardware übertragen, um eine Abstraktion vom physischen FPGA zu erreichen und diesen möglichst effizient auslasten zu können. Das Ziel besteht hierbei darin, mehrere unabhängige, nebenläufig arbeitende Nutzerkerne auf demselben physischen FPGA zu realisieren und durch Migration auf andere Rechenknoten zu übertragen sowie von der physischen Größe und der Architektur des FPGAs zu abstrahieren. Dabei wird nicht nur der FPGA virtualisiert, sondern – anders als bei der Mehrzahl vergleichbarer Arbeiten – das Gesamtsystem und der Einsatzzweck berücksichtigt. Ein prototypisch entwickeltes Cloud-System wurde im Rahmen mehrerer Projekte evaluiert. Durch diese prototypische Umsetzung wird nachgewiesen, dass eine FPGA-Virtualisierung auf aktuellen FPGAs möglich ist und welche Kosten dazu erforderlich sind. Ebenso zeigt sich, dass aufgrund bestimmter fester Strukturen eine Etablierung von homogenen Bereichen notwendig ist, um die Migration eines partiellen FPGA-Kontextes zu ermöglichen und eine effiziente Lastverteilung in der Cloud zu realisieren. Die prototypische Implementierung zeigt, dass eine Migration mit aktuellen FPGA-Architekturen möglich, aber mit Kosten in Form von FPGA-Ressourcen verbunden ist. Des Weiteren wird mittels Simulation untersucht, ob die in einem komplexen Anwendungsszenario angewendete Migration auch in einem größeren Cloud-System zu einer effizienteren Auslastung der Ressourcen beitragen kann. Zusammenfassend ist sowohl durch die entwickelte Virtualisierung als auch durch die Möglichkeit einer Migration die Einsparung von Hardware-Ressourcen und somit auch Energie in einem modernen Cloud-System möglich.

[ES] En los últimos años, la fotónica integrada programable ha evolucionado desde considerarse un paradigma nuevo y prometedor para implementar la fotónica a una escala más amplia hacia convertirse una realidad sólida y revolucionaria, capturando la atención de numerosos grupos de investigación e industrias. Basada en el mismo fundamento teórico que las matrices de puertas lógicas programables en campo (o FPGAs, en inglés), esta tecnología se sustenta en la disposición bidimensional de bloques unitarios de lógica programable (en inglés: PUCs) que -mediante una programación adecuada de sus actuadores de fase- pueden implementar una gran variedad de funcionalidades que pueden ser elaboradas para operaciones básicas o más complejas en muchos campos de aplicación como la inteligencia artificial, el aprendizaje profundo, los sistemas de información cuántica, las telecomunicaciones 5/6-G, en redes de conmutación, formando interconexiones en centros de datos, en la aceleración de hardware o en sistemas de detección, entre otros. En este trabajo, nos dedicaremos a explorar varias aplicaciones software de estos procesadores en diferentes diseños de chips. Exploraremos diferentes enfoques de vanguardia basados en la optimización computacional y la teoría de grafos para controlar y configurar con precisión estos dispositivos. Uno de estos enfoques, la autoconfiguración, consiste en la síntesis automática de circuitos ópticos -incluso en presencia de efectos parasitarios como distribuciones de pérdidas no uniformes a lo largo del diseño hardware, o bajo interferencias ópticas y eléctricas- sin conocimiento previo sobre el estado del dispositivo. Hay ocasiones, sin embargo, en las que el acceso a esta información puede ser útil. Las herramientas de autocalibración y autocaracterización nos permiten realizar una comprobación rápida del estado de nuestro procesador fotónico, lo que nos permite extraer información útil como la corriente eléctrica que suministrar a cada actuador de fase para cambiar el estado de su PUC correspondiente, o las pérdidas de inserción de cada unidad programable y de las interconexiones ópticas que rodean a la estructura. Estos mecanismos no solo nos permiten identificar rápidamente cualquier PUC o región del chip defectuosa en nuestro diseño, sino que también revelan otra alternativa para programar circuitos fotónicos en nuestro diseño a partir de valores de corriente predefinidos. Estas estrategias constituyen un paso significativo para aprovechar todo el potencial de estos dispositivos. Proporcionan soluciones para manejar cientos de variables y gestionar simultáneamente múltiples acciones de configuración, una de las principales limitaciones que impiden que esta tecnología se extienda y se convierta en disruptiva en los próximos años. / [CA] En els darrers anys, la fotònica integrada programable ha evolucionat des de considerarse un paradigma nou i prometedor per implementar la fotònica a una escala més ampla cap a convertir-se en una realitat sòlida i revolucionària, capturant l'atenció de nombrosos grups d'investigaciò i indústries. Basada en el mateix fonament teòric que les matrius de portes lògiques programable en camp (o FPGAs, en anglès), aquesta tecnología es sustenta en la disposición bidimensional de blocs units lògics programables (en anglès: PUCs) que -mitjançant una programación adequada dels seus actuadors de fase- poden implementar una gran varietat de funcionalitats que poden ser elaborades per a operacions bàsiques o més complexes en molts camps d'aplicació com la intel·ligència artificial, l'aprenentatge profund, els sistemes d'informació quàntica, les telecomunicacions 5/6-G, en xarxes de comutació, formant interconnexions en centres de dades, en l'acceleració de hardware o en sistemes de detecció, entre d'altres. En aquest treball, ens dedicarem a explorar diverses capatitats de programari d'aquests processadors en diferents dissenys de xips. Explorem diferents enfocaments de vanguardia basats en l'optimització computacional i la teoría de grafs per controlar i configurar amb precisió aquests dispositius. Un d'aquests enfocaments, l'autoconfiguració, tracta de la síntesi automática de circuits òptics -fins i tot en presencia d'efectes parasitaris com ara pèrdues no uniformes o crosstalk òptic i elèctric- sense cap coneixement previ sobre l'estat del dispositiu. Tanmateix, hi ha ocasions en les quals l'accés a aquesta información pot ser útil. Les eines d'autocalibració i autocaracterització ens permeten realizar una comprovació ràpida de l'estat del nostre procesador fotònic, el que ens permet obtener informació útil com la corrent eléctrica necessària per alimentar cada actuador de fase per canviar l'estat del seu PUC corresponent o la pèrdua d'inserció de cada unitat programable i de les interconnexions òptiques que envolten l'estructura. Aquests mecanisms no només ens permeten identificar ràpidament qualsevol PUC o área del xip defectuosa en el nostre disseny , sinó que també ens mostren una altra alternativa per programar circuits fotònics en el nostre disseny a partir de valors de corrent predefinits. Aquestes estratègies constitueixen un pas gegant per a aprofitar tot el potencial d'aquests dispositius. Proporcionen solucions per a gestionar centenars de variables i alhora administrar múltiples accions de configuració, una de les principals limitacions que impideixen que aquesta tecnología esdevingui disruptiva en els pròxims anys. / [EN] In recent years, programmable integrated photonics (PIP) has evolved from a promising, new paradigm to deploy photonics to a larger scale to a solid, revolutionary reality, bringing up the attention of numerous research and industry players. Based on the same theoretical foundations than field-programmable gate arrays (FPGAs), this technology relies on common, two-dimensional integrated optical hardware configurations based on the interconnection of programmable unit cells (PUCs), which -by suitable programming of their phase actuators- can implement a variety of functionalities that can be elaborated for basic or more complex operation in many application fields, such as artificial intelligence, deep learning, quantum information systems, 5/6-G telecommunications, switching, data center interconnections, hardware acceleration and sensing, amongst others. In this work, we will dedicate ourselves to explore several software capabilities of these processors under different chip designs. We explore different cutting-edge approaches based on computational optimization and graph theory to precisely control and configure these devices. One of these, self-configuration, deals with the automated synthesis of optical circuit configurations -even in presence of parasitic effects such as nonuniform losses, optical and electrical crosstalk- without any need for prior knowledge about hardware state. There are occasions, though, in which accessing to this information may be of use. Self-calibration and self-characterization tools allow us to perform a quick check to our photonic processor's status, allowing us to retrieve useful pieces of information such as the electrical current needed to supply to each phase actuator to change its corresponding PUC state arbitrarily or the insertion loss of every unit cell and optical interconnection surrounding the structure. These mechanisms not only allow us to quickly identify any malfunctioning PUCs or chip areas in our design, but also reveal another alternative to program photonic circuits in our design from current pre-sets. These strategies constitute a gigantic step to unleash all the potential of these devices. They provide solutions to handle with hundreds of variables and simultaneously manage multiple configuration actions, one of the main limitations that prevent this technology to scale up and become disruptive in the years to come. / López Hernández, A. (2023). Multipurpose Programmable Integrated Photonics: Principles and Applications [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/196867

The Frequency Disturbance Recorder (FDR) is a specialized data acquisition device designed to monitor fluctuations in the overall power system. The device is designed such that it can be attached by way of a standard wall power outlet to the power system. These devices then transmit their calculated frequency data through the public internet to a centralized data management and storage server. By distributing a number of these identical systems throughout the three major North American power systems, Virginia Tech has created a Frequency Monitoring Network (FNET). The FNET is composed of these distributed FDRs as well as an Information Management Server (IMS). Since frequency information can be used in many areas of power system analysis, operation and control, there are a great number of end uses for the information provided by the FNET system. The data provides researchers and other users with the information to make frequency analyses and comparisons for the overall power system. Prior to the end of 2004, the FNET system was made a reality, and a number of FDRs were placed strategically throughout the United States. The purpose of this thesis is to present the elements of a new generation of FDR hardware design. These elements will enable the design to be more flexible and to lower reliance on some vendor specific components. Additionally, these enhancements will offload most of the computational processing required of the system to a commodity PC rather than an embedded system solution that is costly in both development time and financial cost. These goals will be accomplished by using a Field Programmable Gate Array (FPGA), a commodity off-the-shelf personal computer, and a new overall system design. / Master of Science

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / As the rates and numbers of serial telemetry data streams increase, the cost of timely, efficient and robust distribution of those streams increases faster. Without alternatives to traditional pointto- point serial distribution, the complexity of the infrastructure will soon overwhelm potential benefits of the increased stream counts and rates. Utilization of multiplexing algorithms in Field- Programmable Gate Arrays (FPGA), coupled with universally available Internet Protocol (IP) switching technology, provides a low-latency, time-data correlated multi-stream distribution solution. This implementation has yielded zero error IP transport and regeneration of multiple serial streams, maintaining stream to stream skew of less than 10 nsec, with end-to-end latency contribution of less than 15 msec. Adoption of this technique as a drop-in solution can greatly reduce the costs and complexities of maintaining pace with the changing serial telemetry community.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / We describe the design and development of a baseband telemetry system for multistage launch vehicles. The system is organized as a three tier one with remote data acquisition and processing units and a centralized control unit. The front-end Data Acquisition Units (DAUs) feature software programmable amplification, offset, filtering and sensor excitation and thus are flexible to interface directly to a variety of sensors used in launch vehicles. The Data Processing Units (DPUs) gather data from DAUs through a serial link compatible to RS-485 standards and carry out a variety of data analysis and data compression functions on selected channels under software control. The central Telemetry Control Unit (TCU) receives this data through a transformer isolated link compatible to MIL-1553B standards and performs the functions of data delay, data storage, onboard computer data monitoring, PCM formatting and pre-modulation signal conditioning to achieve miniaturization. The configuration and features of this telemetry system make its integration simple without compromising on data integrity and reliability and suit the adoption of futuristic technologies and concepts such as smart sensor networks, adaptability, reconfiguration and vehicle health management.

Denna rapport omfattar ett 15 poängs (22,5 högskolepoäng) examensarbete vid Karlstads universitet. Arbetet har utförts på plats hos BAE Systems Bofors i Karlskoga. Företaget ville kunna styra en radiostyrd leksaksstridsvagn med en laserpekare. En kamera ansluten till en digital signalprocessor (DSP) skulle kunna detektera var en laserpunkt befinner sig och styra stridsvagnen mot den. Ett styrgränssnitt mellan DSP:n och leksaksstridsvagnen konstruerades och byggdes med hjälp av en programmerbar logisk krets. Leksaksstridsvagnens interna signalsystem analyserades. En manchesterkodad signal i form av ett 32-bitars seriellt kodord hittades, vilket ursprungligen kom från radiostyrningen. Ett styrgränssnitt konstruerades kring en CPLD (Complex Programmable Logic Device) vilken programmerades med VHDL (Very high speed integrated Hardware Description Language) som återskapar den Manchesterkodade styrsignalen. Gränssnittet ansluter till DSP:n som kontrollerar stridsvagnens styrning och övriga funktioner till fullo. Kommunikationen mellan styrgränssnittet och DSP:n sker via ett parallellgränssnitt som är 16-bitar brett. 13 bitar är datasignaler och övriga tre är ”styrbitar” som konfigurerar gränssnittet. En applikation integrerades i projektet för att demonstrera styrgränssnittets funktion. DSP:n tolkar var en laserpunkt befinner sig inom ett kameraområde och skickar motsvarande styrsignaler till leksaksstridsvagnen. / This report consists of a 15 points (22.5 ECTS) Exam Degree project at Karlstad University. The work was done on location at BAE Systems Bofors AB in Karlskoga. The company wanted to control a radio controlled toy tank from a digital signal processor (DSP). A camera connected to the DSP locates the laser point and steers the toy tank towards it. An interface using a programmable logic device was constructed that connects the DSP to the toy tank. The internal signals in the toy tank was analyzed and a Manchester coded signal in form of a 32-bit serial code word was detected. The code word originated from the radio controller. The control interface was built around a CPLD (Complex Programmable Logic Device) which was programmed in VHDL (Very high speed integrated Hardware Description Language). The control interface recreates the signal controlling the toy tank. The interface connects the toy tank to the DSP which controls the toy tank and it’s functions to the full extent. Communication between the interface and the DSP is done via a 16 bit parallel connection. 13 of the bits are data bits and the remaining 3 are control bits that are used to set up the interface. An application was integrated in the project where the DSP is detecting a laser point. Corresponding signals to the laser points position where sent to the control interface to demonstrate the function of the interface.

ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / Multiple-Input Multiple-Output (MIMO) systems have at least two transmitting antennas, each generating unique signals. However some applications may require three, four, or more transmitting devices to achieve the desired system performance. This paper describes the design of a scalable MIMO transmitter, based on field programmable gate array (FPGA) technology. Each module contains a FPGA, and associated digital-to-analog converters, I/Q modulators, and RF amplifiers needed to power one of the MIMO transmitters. The system was designed to handle up to a 10 Mbps data rate, and transmit signals in the unlicensed 2.4 GHz ISM band.

No description available.

The shopping trolley have been frequently used in our daily life. However, the hygiene condition of cart makes people worry a lot, especially the handle brothers. Nowadays, several methods have been proposed to clean the shopping carts but considered uneconomic and inflexible. In this study, we aim to design an integrated cart washing system based on a trailer applied to medium or small supermarket. This system should be more efficient, economic, easily to operate, safer and les water consummation. The integrated cart washing system has three basic functions of washing, disinfection and drying. The system is controlled by PLC program, all steps in the cleaning process are fully automatic insider the trailer and each component are adjustable according to various shopping carts. The system only requires one person to operate and it costs 30 seconds to wash a single cart, able to wash up to 120 cart/hour. Disinfection and drying steps provide high washing quality. Moreover, water-recycling design can save part of wasted water. The modelling and assembly was designed in Autodesk Inventor 2016, the hardware design circuit-writing diagram was performed in AutoCAD, the software design of Programmable logic controller (PLC) was made in STEP 7-Micro/Win. Theoretical calculation and simulation prove the safety and possibility of our system. We concluded that this system might have commercial interests in the market.