Devido às necessidades do mundo moderno, os sistemas de automação têm aumentado sua complexidade, fazendo com que sejam desenvolvidas ferramentas de engenharia cada vez mais poderosas para modelá-los e analisá-los. Em sistemas de automação industrial, os Controladores Lógicos Programáveis (CLPs) têm sido amplamente empregados. Os CLPs são geralmente programados por meio da linguagem de programação Ladder, uma das cinco linguagens definidas pela IEC 61131-3. Entretanto, apesar da linguagem de programação Ladder ser flexível e de fácil aprendizado por parte dos usuários, ela apresenta limitações quanto à: detecção de erros no algoritmo de controle do sistema de automação; torna as modificações muito trabalhosas e não possibilita a simulação, análise de performance e análise operacional do sistema. Este trabalho de pesquisa apresenta o desenvolvimento e os testes da metodologia denominada MARPASI - Metodologia de Aplicação das Redes de Petri em Automação de Sistemas Industriais. Como o desenvolvimento da MARPASI foi efetuado baseado na teoria de Redes de Petri, este trabalho também apresenta uma revisão bibliográfica sobre o tema de aplicação de Redes de Petri para a programação de CLP. A MARPASI possibilita analisar um sistema de automação por meio das Redes de Petri e na geração da linguagem de programação Ladder. Portanto, o emprego da MARPASI contribui para a otimização do processo de engenharia de automação e também para a programação mais eficiente de CLPs. / Due to the needs of the modern world, the systems of automation have increased their complexity, forcing the development of ever more powerful engineering tolls to shape and analyse them. In systems of industrial automation, the Programmable Logic Controllers (PLCs), have been widely applies. The PLCs are generally programmed through the use of the Ladder programming language, one of the five languages defined by the IEC 61131-3. Unfortunately, while the Ladder programming language is flexible, and easily learned by its users, it evinces limitations concerning: error detection in the control algorithm of the automation system: makes modifications very laborious and does not allow any simulation, performance analysis and operational systems analysis. This study presents the development and tests of the methodology denominated as MARPASI - Methodology of the application of Petri Net in the automation of industrial systems. Since the development of MARPASI was made based on Petri Net Theory, this study also presents a bibliographic review about the theme of the application of Petri Net for the programming of PLC. MARPASI makes it possible to analyse a system of automation through Petri Net and in the generation of the Ladder programming language. Because of these, the utilization of MARPASI contributes for capacities, the optimization of automation engineering processes, and also for a more efficient programming of the PLCs.

Este trabalho traça um panorama dos PLCs e tecnologias associadas em momentos anteriores e posteriores à publicação da norma IEC61131-3 e discute aspectos relativos à sua adoção. A aplicação deste norma pode trazer ganhos de produtividade no projeto e implementação de sistemas de automação industrial. Esta dissertação apresenta o caso do "Projeto de modernização dos navios-varredores da Marinha do Brasil" no qual alguns dos conceitos desta norma foram utilizados com sucesso. Ferramentas e metodologias desenvolvidas para adequar o PLC existente a alguns requisitos da norma são descritas ao longo da dissertação. A operação do novo sistema de varredura pode ser verificada através dos resultados experimentais apresentados. / This work presents an overview of the PLC and associated technologies before and after the publication of the IEC61131-3 standard. Some aspects concerning the adoption of this standard are also discussed. The application of this standard can increase productivity in the design and implementation of industrial automation systems. Some concepts of this standard were applied, succesfully, to the modernization of the Brazilian Navy mine-sweepers. Tools and methods that were required in order to adapt the existing PLC to the IEC standard are described. The operation of the newly developed system can be verified by experimental results.

Leong Monk Ping. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (p. 255-278). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

by Xue-jie Zhang. / "December 1999." / Thesis (Ph.D.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (p. 144-[152]). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Field Programmable Gate Array (FPGA) has a dominating market in digital system prototyping and reconfigurable computing. To make a flexible and efficient FPGA chip both the hardware architecture and the design tool should be further engineered. An innovative architecture always requires excellent development of EDA tools to fully explore the intrinsic merits of the hardware. / FPGA Technology Mapping is an important design automation problem which affects placement and routing dramatically. Depth-optimal technology mapping algorithms were proposed and produced quality mapping solution for delay minimization. However such algorithms have not yet considered to further reduce area consumption using the powerful logic transformation techniques. / On hardware side, we present a study on the effect of direct and fast routing hard-wires in FPGA routing architecture. Based on the routing pattern analyzed from real routing data, we proposed a so-called shortcut -based routing to handle short and localized routing requirements. Experimental results show that the shortcuts are well utilized and it allows a better average wirelength usage in the whole routing architecture. / On software side, we propose a versatile approach to combine logic transformation and technology mapping. In addition to a level-reduction scheme, we also present a method of reducing the number of LUTs used while keeping the depth optimality. Our approach is based on a greedy but effective heuristic to choose good alternative wires for transformation. Large number of experiments were conducted to analyze the effectiveness of the system. Our results show that our approach can effectively reduce at least 5% (up to 25%) of the area over initial mapping by various state-of-the-art FPGA technology mappers. Furthermore, we found that the delay performance can be improved by 5% when the area is reduced by our system. / Tang, Wai Chung. / Adviser: David Yu-Liang Wu. / Source: Dissertation Abstracts International, Volume: 70-06, Section: B, page: 3704. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 70-74). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

by Lo Wing-yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves vii-ix). / ABSTRACT --- p.i / LIST OF TABLES --- p.iv / LIST OF FIGURES --- p.v / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Traditional Design Prototyping --- p.1 / Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2 / Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5 / Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6 / Chapter 2. --- HARDWARE DESIGNS --- p.9 / Chapter 2.1 --- Bus Interconnection --- p.9 / Chapter 2.1.1 --- Fixed buses --- p.9 / Chapter 2.1.2 --- Programmable buses --- p.12 / Chapter 2.2 --- Architectural Features --- p.15 / Chapter 2.2.1 --- Field programmable gate array --- p.15 / Chapter 2.2.2 --- Microprocessor --- p.15 / Chapter 2.2.3 --- Memory --- p.16 / Chapter 2.2.4 --- Buffers --- p.18 / Chapter 3. --- SOFTWARE TOOLS --- p.20 / Chapter 3.1 --- Critical Path Analysis --- p.20 / Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21 / Chapter 3.1.2 --- Computation time --- p.21 / Chapter 3.2 --- Circuit Partitioning --- p.23 / Chapter 3.2.1 --- Partitioning algorithm --- p.24 / Chapter 3.2.2 --- Effects of partitioning --- p.36 / Chapter 3.2.3 --- Partitioning parameters --- p.38 / Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39 / Chapter 3.3 --- IO Assignments --- p.40 / Chapter 3.3.1 --- Connect 4 FPGAs --- p.40 / Chapter 3.3.2 --- Connect 3 FPGAs --- p.42 / Chapter 3.3.3 --- Connect 2 FPGAs --- p.44 / Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47 / Chapter 3.4 --- Other Tools --- p.48 / Chapter 4. --- STRUCTURE ANALYSIS --- p.49 / Chapter 5. --- RESULTS --- p.52 / Chapter 6. --- FUTURE DIRECTION --- p.73 / Chapter 6.1 --- Other Possible Configurations --- p.73 / Chapter 6.2 --- Programmable Interconnection --- p.73 / Chapter 6.3 --- Expandability of UPB --- p.74 / Chapter 7. --- CONCLUSION --- p.75 / BIBLIOGRAPHY --- p.vii / APPENDICES --- p.x

Cheung Yu Hoi Ocean. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 65-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.2 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Outline --- p.3 / Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4 / Chapter 2.3 --- Secure Virtual Private Network --- p.6 / Chapter 2.4 --- LibDES --- p.9 / Chapter 2.5 --- FreeS/WAN --- p.9 / Chapter 2.6 --- Commercial VPN solutions --- p.9 / Chapter 2.7 --- Summary --- p.11 / Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12 / Chapter 3.1 --- Introduction --- p.12 / Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12 / Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14 / Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16 / Chapter 3.3 --- The IDEA Algorithm --- p.17 / Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20 / Chapter 3.3.2 --- Previous work on IDEA --- p.21 / Chapter 3.4 --- Block Cipher Modes of operation --- p.23 / Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23 / Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25 / Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27 / Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27 / Chapter 3.6 --- Pilchard --- p.30 / Chapter 3.6.1 --- Memory Cache Control Mode --- p.31 / Chapter 3.7 --- Electronic Design Automation Tools --- p.32 / Chapter 3.8 --- Summary --- p.33 / Chapter 4 --- Implementation / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Hardware Platform --- p.36 / Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36 / Chapter 4.1.3 --- Pilchard Software --- p.38 / Chapter 4.2 --- DES in ECB mode --- p.39 / Chapter 4.2.1 --- Hardware --- p.39 / Chapter 4.2.2 --- Software Interface --- p.40 / Chapter 4.3 --- DES in CBC mode --- p.42 / Chapter 4.3.1 --- Hardware --- p.42 / Chapter 4.3.2 --- Software Interface --- p.42 / Chapter 4.4 --- Triple-DES in CBC mode --- p.45 / Chapter 4.4.1 --- Hardware --- p.45 / Chapter 4.4.2 --- Software Interface --- p.45 / Chapter 4.5 --- IDEA in ECB mode --- p.48 / Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48 / Chapter 4.5.2 --- Hardware --- p.48 / Chapter 4.5.3 --- Software Interface --- p.50 / Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51 / Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52 / Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53 / Chapter 4.9 --- Summary --- p.54 / Chapter 5 --- Results --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Benchmarking environment --- p.55 / Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56 / Chapter 5.3.1 --- Performance of Triple-DES core --- p.55 / Chapter 5.3.2 --- Performance of IDEA core --- p.58 / Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59 / Chapter 5.4.1 --- Triple-DES --- p.59 / Chapter 5.4.2 --- IDEA --- p.60 / Chapter 5.5 --- Summary --- p.61 / Chapter 6 --- Conclusion --- p.62 / Chapter 6.1 --- Future development --- p.63 / Bibliography --- p.65

A vast majority of electronic systems including medical, surveillance and critical infrastructure employs image processing to provide intelligent analysis. They use onboard pre-processing to reduce data bandwidth and memory requirements before sending information to the central system. Field Programmable Gate Arrays (FPGAs) represent a strong platform as they permit reconfigurability and pipelining for streaming applications. However, rapid advances and changes in these application use cases crave adaptable hardware architectures that can process dynamic data workloads and be easily programmed to achieve ecient solutions in terms of area, time and power. FPGA-based development needs iterative design cycles, hardware synthesis and place-and-route times which are alien to the software developers. This work proposes an FPGA-based programmable hardware acceleration approach to reduce design effort and time. This allows developers to use FPGAs to profile, optimise and quickly prototype algorithms using a more familiar software-centric, edit-compile-run design flow that enables the programming of the platform by software rather than high-level synthesis (HLS) engineering principles. Central to the work has been the development of an optimised FPGA-based processor called Image Processing Processor (IPPro) which efficiently uses the underlying resources and presents a programmable environment to the programmer using a dataflow design principle. This gives superior performance when compared to competing alternatives. From this, a three-layered platform has been created which enables the realisation of parallel computing skeletons on FPGA which are used to eciently express designs in high-level programming languages. From bottom-up, these layers represent programming (actor, multiple actors and parallel skeletons) and hardware (IPPro core, multicore IPPro, system infrastructure) abstraction. The platform allows acceleration of parallel and non-parallel dataflow applications. A set of point and area image pre-processing functions are implemented on Avnet Zedboard platform which allows the evaluation of the performance. The point function achieved 2.53 times better performance than the area functions and point and area functions achieved performance improvements of 7.80 and 5.27 times over sin- gle core IPPro by exploiting data parallelism. The pipelined execution of multiple stages revealed that a dataflow graph can be decomposed into balanced actors to deliver maximum performance by hiding data transfer and processing time through exploiting task parallelism; otherwise, the maximum achievable performance is limited by the slowest actor due to the ripple effect caused by unbalanced actors. The platform delivered better performance in terms of fps/Watt/Area than Embedded Graphic Processing Unit (GPU) considering both technologies allows a software-centric design flow.

by Pan Jiao Feng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 89-93). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgments --- p.v / List of Tables --- p.x / List of Figures --- p.xi / Chapter Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Graph definitions --- p.2 / Chapter 1.2 --- The S box graph --- p.2 / Chapter 1.3 --- The file transfer graph --- p.4 / Chapter 1.4 --- "(g, f)-factor and (g, f)-factorization" --- p.5 / Chapter 1.5 --- Thesis contributions --- p.6 / Chapter 1.6 --- Organization of the thesis --- p.7 / Chapter Chapter 2. --- On the Optimal Four-way Switch Box Routing Structures of FPGA Greedy Routing Architectures --- p.8 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.1.1 --- FPGA model and S box model --- p.9 / Chapter 2.1.2 --- FPGA routing --- p.10 / Chapter 2.1.3 --- Problem formulation --- p.10 / Chapter 2.2 --- Definitions and terminology --- p.12 / Chapter 2.2.1 --- General terminology --- p.12 / Chapter 2.2.2 --- Graph definitions --- p.15 / Chapter 2.2.3 --- The S box graph --- p.15 / Chapter 2.3 --- Properties of the S box graph and side-to-side graphs --- p.16 / Chapter 2.3.1 --- On the properties of the S box graph --- p.16 / Chapter 2.3.2 --- The properties of side-to-side graphs --- p.19 / Chapter 2.4 --- Conversion of the four-way FPGA routing problem --- p.23 / Chapter 2.4.1 --- Conversion of the S box model --- p.24 / Chapter 2.4.2 --- Conversion of the DAAA model --- p.26 / Chapter 2.4.3 --- Conversion of the DADA model --- p.27 / Chapter 2.4.4 --- Conversion of the DDDA model --- p.28 / Chapter 2.5 --- Low bounds of routing switches --- p.28 / Chapter 2.5.1 --- The lower bound of the DAAA model --- p.29 / Chapter 2.5.2 --- The lower bound of the DADA model --- p.30 / Chapter 2.5.3 --- The lower bound of the DDDA model --- p.31 / Chapter 2.6 --- Optimal structure of one-side predetermined four-way FPGA routing --- p.32 / Chapter 2.7 --- Optimal structures of two-side and three-side predetermined four-way FPGA routing --- p.45 / Chapter 2.7.1 --- Optimal structure of two-side predetermined four-way FPGA routing --- p.46 / Chapter 2.7.2 --- Optimal structure of three-side predetermined four-way FPGA routing --- p.47 / Chapter 2.8 --- Conclusion --- p.49 / Appendix --- p.50 / Chapter Chapter 3. --- "Application of (0, f)-Factorization on the Scheduling of File Transfers" --- p.53 / Chapter 3.1 --- Introduction --- p.53 / Chapter 3.1.1 --- "(0,f)-factorization" --- p.54 / Chapter 3.1.2 --- File transfer model and its graph --- p.54 / Chapter 3.1.3 --- Previous results --- p.56 / Chapter 3.1.4 --- Our results and outline of the chapter --- p.56 / Chapter 3.2 --- NP-completeness --- p.57 / Chapter 3.3 --- Some lemmas --- p.58 / Chapter 3.4 --- Bounds of file transfer graphs --- p.59 / Chapter 3.5 --- Comparison --- p.62 / Chapter 3.6 --- Conclusion --- p.68 / Chapter Chapter 4. --- "Decomposition Graphs into (g,f)-Factors" --- p.69 / Chapter 4.1 --- Introduction --- p.69 / Chapter 4.1.1 --- "(g,f)-factors and (g,f)-factorizations" --- p.69 / Chapter 4.1.2 --- Previous work --- p.70 / Chapter 4.1.3 --- Our results --- p.72 / Chapter 4.2 --- Proof of Theorem 2 --- p.73 / Chapter 4.3 --- Proof of Theorem 3 --- p.79 / Chapter 4.4 --- Proof of Theorem 4 --- p.80 / Chapter 4.5 --- Related previous results --- p.82 / Chapter 4.6 --- Conclusion --- p.84 / Chapter Chapter 5. --- Conclusion --- p.85 / Chapter 5.1 --- About graph-based approaches --- p.85 / Chapter 5.2 --- FPGA routing --- p.87 / Chapter 5.3 --- The scheduling of file transfer --- p.88 / Bibliography --- p.89 / Vita --- p.94

Elliptic curve cryptosystems offer security comparable to that of traditional asymmetric cryptosystems, such as those based on the RSA encryption and digital signature algorithms, with smaller keys and computationally more efficient algorithms. The ability to use smaller keys and computationally more efficient algorithms than traditional asymmetric cryptographic algorithms are two of the main reasons why elliptic curve cryptography has become popular. As the popularity of elliptic curve cryptography increases, the need for efficient hardware solutions that accelerate the computation of elliptic curve point multiplications also increases. This dissertation introduces elliptic curve processor architectures suitable for the computation of point multiplications for curves defined over fields GF(2^m) and curves defined over fields GF(p). Each of the processor architectures presented here allows designers to tailor the performance and hardware requirements according to their performance and cost goals. Moreover, these architectures are well suited for implementation in modern field programmable gate arrays (FPGAs). This point was proved with prototyped implementations. The fastest prototyped GF(2^m) processor can compute an arbitrary point multiplication for curves defined over fields GF(2^167) in 0.21 milliseconds and the prototyped processor for the field GF(2^192-2^64-1) is capable of computing a point multiplication in about 3.6 milliseconds. The most critical component of an elliptic curve processor is its arithmetic unit. A typical arithmetic unit includes an adder/subtractor, a multiplier, and possibly a squarer. Some of the architectures presented in this work are based on multiplier and squarer architectures developed as part of the work presented in this dissertation. The GF(2^m) least significant bit super-serial multiplier architecture, the GF(2^m) most significant bit super-serial multiplier architecture, and a new GF(p) Montgomery multiplier architecture were developed as part of this work together with a new squaring architecture for GF(2^m).