With the rise of the Internet of Things and the proliferation of embedded devices equipped with an accelerator arose a need for efficient resource utilization. Hardware acceleration is a complex topic that requires specialized domain knowledge about the platform and different trade-offs that have to be made, especially in the area of power consumption. Efficient work offloading strives to reduce or at least maintain the total power consumption of the system. Offloading packet capturing is usually done in more powerful devices, hence scarce research is present concerning network packet acceleration in embedded devices. The thesis focuses on accelerating networking packets utilizing a Field Programmable Gate Array in an embedded Linux System. The solution is based on a custom Linux distribution assembled using the Buildroot tool, specially configured and patched Linux kernel, uboot bootloader, and the programmable logic for packet acceleration. The system is evaluated on a De0-Nano System on Chip development board through modifications to burst lengths, packet sizes, and programmable logic clock frequency. Metrics include packet capturing time, time per packet, and consumed power. Finally, the results are contrasted with baseline embedded Linux packet processing by inspection of a packet’s path through the kernel. Collected results provide a deeper understanding of the packet acceleration problem in embedded devices and the resultant system gives a solid starting point for possible extensions such as packet filtering. Key findings include an improvement in packet processing speed as the clock frequency and burst length are increased while maintaining power consumption. Additionally, the solution performs better when the packet sizes are above 64 bytes as the overhead of additional logic necessary for their processing is compensated. The project is also found to be significantly faster than regular in kernel processing with the caveat of providing just packet capturing whereas Linux contains a full network stack. / I och med uppkomsten av sakernas internet och spridningen av inbyggda enheter som är utrustade med en accelerator har det uppstått ett behov av effektivt resursutnyttjande. Hårdvaruacceleration är ett komplext ämne som kräver specialiserad domänkunskap om plattformen och olika avvägningar som måste göras, särskilt när det gäller energiförbrukning. Effektiv arbetsavlastning strävar efter att minska eller åtminstone bibehålla systemets totala energiförbrukning. Avlastning av paketering sker vanligtvis i kraftfullare enheter, och därför finns det knappt någon forskning om nätverksacceleration av paket i inbyggda enheter. Avhandlingen är inriktad på att påskynda nätverkspaket med hjälp av en Field Programmable Gate Array i ett inbäddat Linuxsystem. Lösningen bygger på en anpassad Linuxdistribution som sammanställts med hjälp av verktyget Buildroot, en särskilt konfigurerad och patchad Linuxkärna, uboot bootloader och den programmerbara logiken för paketacceleration. Systemet utvärderas på ett De0-Nano System on Chip-utvecklingskort genom ändringar av burstlängder, paketstorlekar och den programmerbara logikens klockfrekvens. Metrikerna omfattar tid för paketering, tid per paket och förbrukad effekt. Slutligen jämförs resultaten med grundläggande inbäddad Linux-paketbehandling genom inspektion av paketens väg genom kärnan. De samlade resultaten ger en djupare förståelse för problemet med paketacceleration i inbyggda enheter och det resulterande systemet ger en solid utgångspunkt för möjliga utvidgningar, t.ex. paketfiltrering. Bland de viktigaste resultaten kan nämnas en förbättring av hastigheten i paketbehandlingen när klockfrekvensen och burstlängden ökas samtidigt som strömförbrukningen bibehålls. Dessutom fungerar lösningen bättre när paketstorleken är större än 64 bytes eftersom den extra logik som krävs för att behandla paketen kompenseras. Projektet har också visat sig vara betydligt snabbare än vanlig kärnbearbetning, med den reservationen att det bara tillhandahåller paketupptagning, medan Linux innehåller en fullständig nätverksstack. / Rozwój Internetu Rzeczy i ąrosnca śćpopularno systemów wbudowanych ąposiadajcych wbudowany akcelerator ęsprztowy łsprawiy, że łwzrosa potrzeba na ich efektywne wykorzytanie. Akceleracja ęsprztowa jest ądziedzin nauki, która wymaga specjalistycznej wiedzy na temat platformy na której ma ćoperowa oraz wymaga śznajomoci potencjalnych komplikacji które ęsi z ąni ążąwi. Efektywna akceleracja ma na celu ęredukcj żzuycia energii, a przynajmnniej jej utrzymanie na dotychczasowym poziomie. Tematyka ta jest śćdo uboga pod ąktem ędostpnej literatury, żgdy zazwyczaj akceleratory stosowane do sieciowych ąńrozwiza ąs żuywane w ąrozwizaniach serwerowych gdzie ęąwystpuj innego rodzaju problemy. W pracy wykorzystany jest akcelerator Field Programmable Gate Array który jest ęśączci łpytki deweloperskiej De0-Nano System on Chip, gdzie łdziaa łąwspópracujc z wbudowanym systemem Linux, do którego przygotowania wykorzystano ęnarzdzie Buildroot. Na ńkocowe ąrozwizanie ponadto łskada ęsi łpoatane ąjdro Linuxa, bootloader uboot oraz programowalna logika ąrealizujca przechwytywanie pakietów sieciowych. ąRozwizanie poddane jest testom, w których parametry odpowiedzialne za łśćdugo transakcji typu burst, rozmiaru pakietu oraz ęśczstotliwoci zegara ąs poddawane modyfikacjom. Wyniki ąs przedstawione za ąpomoc czasu przetwarzania pakietu, czasu per pakiet oraz żzuycia mocy. Do oceny śefektywnoci ąrozwizania łżłposuyo żtake porównanie z czasem procesowania pakietu w niezmodyfikowanym systemie Linux Na podstawie eksperymentów dokonanych w pracy ęwysunite ąs ęąnastpujce wnioski: wraz ze wzrostem ęśczstotliwoci zegara oraz łśdugoci transakcji burst, czas procesowania pakietów maleje a żzuycie ąprdu pozostaje na dotychczasowym poziomie. Pakiety o rozmiarze ąprzekraczajcym 64 bajty ąs procesowane wydajniej w dostarczonym ąrozwizaniu poprzez ękompensacj dodatkowego łnakadu czasu narzuconego przez ęlogik ąąązarzdzajc przetwarzaniem. System porównano żtake do łzwykego przetwarzania pakietów ąodbywajcego ęsi w systemie Linux które łokazao ęsi zdecydowanie wolniejsze z żzastrzeeniem, żi ów system dokonuje łpenego przetworzenia pakietów a ąrozwizanie w pracy jedynie ich przechwytywania. Projekt stanowi ępodstaw do ewentualnych ńrozszerze, na łprzykad filtrowania pakietów. Wnioski ęwysunite łżąsu łępogbieniu wiedzy w domenie sieci wbudowanych systemów Linux oraz ęsprztowej akceleracji.

Background: The irradiation of cancer patients with charged particles, mainly protons and carbon ions, has become an established method for the treatment of specific types of tumors. In comparison with the use of X-rays or gamma-rays, particle therapy has the advantage that the dose distribution in the patient can be precisely controlled. Tissue or organs lying near the tumor will be spared. A verification of the treatment plan with the actual dose deposition by means of a measurement can be done through range assessment of the particle beam. For this purpose, prompt gamma-rays are detected, which are emitted by the affected target volume during irradiation. Motivation: The detection of prompt gamma-rays is a task related to radiation detection and measurement. Nuclear applications in medicine can be found in particular for in vivo diagnosis. In that respect the spatially resolved measurement of gamma-rays is an essential technique for nuclear imaging, however, technical requirements of radiation measurement during particle therapy are much more challenging than those of classical applications. For this purpose, appropriate instruments beyond the state-of-the-art need to be developed and tested for detecting prompt gamma-rays. Hence the success of a method for range assessment of particle beams is largely determined by the implementation of electronics. In practice, this means that a suitable detector material with adapted readout electronics, signal and information processing, and data interface must be utilized to solve the challenges. Thus, the parameters of the system (e.g. segmentation, time or energy resolution) can be optimized depending on the method (e.g. slit camera, time-of-flight measurement or Compton camera). Regardless of the method, the detector system must have a high count rate capability and a large measuring range (>7 MeV). For a subsequent evaluation of a suitable method for imaging, the mentioned parameters may not be restricted by the electronics. Digital signal processing is predestined for multipurpose tasks, and, in terms of the demands made, the performance of such an implementation has to be determined. Materials and methods: In this study, the instrumentation of a detector system for prompt gamma-rays emitted during particle therapy is limited to the use of a cadmium zinc telluride (CdZnTe, CZT) semiconductor detector. The detector crystal is divided into an 8x8 pixel array by segmented electrodes. Analog and digital signal processing are exemplarily tested with this type of detector and aims for application of a Compton camera to range assessment. The electronics are implemented with commercial off-the-shelf (COTS) components. If applicable, functional units of the detector system were digitalized and implemented in a field-programmable gate array (FPGA). An efficient implementation of the algorithms in terms of timing and logic utilization is fundamental to the design of digital circuits. The measurement system is characterized with radioactive sources to determine the measurement dynamic range and resolution. Finally, the performance is examined in terms of the requirements of particle therapy with experiments at particle accelerators. Results: A detector system based on a CZT pixel detector has been developed and tested. Although the use of an application-specific integrated circuit is convenient, this approach was rejected because there was no circuit available which met the requirements. Instead, a multichannel, compact, and low-noise analog amplifier circuit with COTS components has been implemented. Finally, the 65 information channels of a detector are digitized, processed and visualized. An advanced digital signal processing transforms the traditional approaches of nuclear electronics in algorithms and digital filter structures for an FPGA. With regard to the characteristic signals (e.g. varying rise times, depth-dependent energy measurement) of a CZT pixel detector, it could be shown that digital pulse processing results in a very good energy resolution (~2% FWHM at 511 keV), as well as permits a time measurement in the range of some tens of nanoseconds. Furthermore, the experimental results have shown that the dynamic range of the detector system could be significantly improved compared to the existing prototype of the Compton camera (~10 keV..7 MeV). Even count rates of ~100 kcps in a high-energy beam could be ultimately processed with the CZT pixel detector. But this is merely a limit of the detector due to its volume, and not related to electronics. In addition, the versatility of digital signal processing has been demonstrated with other detector materials (e.g. CeBr3). With foresight on high data throughput in a distributed data acquisition from multiple detectors, a Gigabit Ethernet link has been implemented as data interface. Conclusions: To fully exploit the capabilities of a CZT pixel detector, a digital signal processing is absolutely necessary. A decisive advantage of the digital approach is the ease of use in a multichannel system. Thus with digitalization, a necessary step has been done to master the complexity of a Compton camera. Furthermore, the benchmark of technology shows that a CZT pixel detector withstands the requirements of measuring prompt gamma-rays during particle therapy. The previously used orthogonal strip detector must be replaced by the pixel detector in favor of increased efficiency and improved energy resolution. With the integration of the developed digital detector system into a Compton camera, it must be ultimately proven whether this method is applicable for range assessment in particle therapy. Even if another method is more convenient in a clinical environment due to practical considerations, the detector system of that method may benefit from the shown instrumentation of a digital signal processing system for nuclear applications. / Hintergrund: Die Bestrahlung von Krebspatienten mit geladenen Teilchen, vor allem Protonen oder Kohlenstoffionen, ist mittlerweile eine etablierte Methode zur Behandlung von speziellen Tumorarten. Im Vergleich mit der Anwendung von Röntgen- oder Gammastrahlen hat die Teilchentherapie den Vorteil, dass die Dosisverteilung im Patienten präziser gesteuert werden kann. Dadurch werden um den Tumor liegendes Gewebe oder Organe geschont. Die messtechnische Verifikation des Bestrahlungsplans mit der tatsächlichen Dosisdeposition kann über eine Reichweitenkontrolle des Teilchenstrahls erfolgen. Für diesen Zweck werden prompte Gammastrahlen detektiert, die während der Bestrahlung vom getroffenen Zielvolumen emittiert werden. Fragestellung: Die Detektion von prompten Gammastrahlen ist eine Aufgabenstellung der Strahlenmesstechnik. Strahlenanwendungen in der Medizintechnik finden sich insbesondere in der in-vivo Diagnostik. Dabei ist die räumlich aufgelöste Messung von Gammastrahlen bereits zentraler Bestandteil der nuklearmedizinischen Bildgebung, jedoch sind die technischen Anforderungen der Strahlendetektion während der Teilchentherapie im Vergleich mit klassischen Anwendungen weitaus anspruchsvoller. Über den Stand der Technik hinaus müssen für diesen Zweck geeignete Instrumente zur Erfassung der prompten Gammastrahlen entwickelt und erprobt werden. Die elektrotechnische Realisierung bestimmt maßgeblich den Erfolg eines Verfahrens zur Reichweitenkontrolle von Teilchenstrahlen. Konkret bedeutet dies, dass ein geeignetes Detektormaterial mit angepasster Ausleseelektronik, Signal- und Informationsverarbeitung sowie Datenschnittstelle zur Problemlösung eingesetzt werden muss. Damit können die Parameter des Systems (z. B. Segmentierung, Zeit- oder Energieauflösung) in Abhängigkeit der Methode (z.B. Schlitzkamera, Flugzeitmessung oder Compton-Kamera) optimiert werden. Unabhängig vom Verfahren muss das Detektorsystem eine hohe Ratenfestigkeit und einen großen Messbereich (>7 MeV) besitzen. Für die anschließende Evaluierung eines geeigneten Verfahrens zur Bildgebung dürfen die genannten Parameter durch die Elektronik nicht eingeschränkt werden. Eine digitale Signalverarbeitung ist für universelle Aufgaben prädestiniert und die Leistungsfähigkeit einer solchen Implementierung soll hinsichtlich der gestellten Anforderungen bestimmt werden. Material und Methode: Die Instrumentierung eines Detektorsystems für prompte Gammastrahlen beschränkt sich in dieser Arbeit auf die Anwendung eines Cadmiumzinktellurid (CdZnTe, CZT) Halbleiterdetektors. Der Detektorkristall ist durch segmentierte Elektroden in ein 8x8 Pixelarray geteilt. Die analoge und digitale Signalverarbeitung wird beispielhaft mit diesem Detektortyp erprobt und zielt auf die Anwendung zur Reichweitenkontrolle mit einer Compton-Kamera. Die Elektronik wird mit seriengefertigten integrierten Schaltkreisen umgesetzt. Soweit möglich, werden die Funktionseinheiten des Detektorsystems digitalisiert und in einem field-programmable gate array (FPGA) implementiert. Eine effiziente Umsetzung der Algorithmen in Bezug auf Zeitverhalten und Logikverbrauch ist grundlegend für den Entwurf der digitalen Schaltungen. Das Messsystem wird mit radioaktiven Prüfstrahlern hinsichtlich Messbereichsdynamik und Auflösung charakterisiert. Schließlich wird die Leistungsfähigkeit hinsichtlich der Anforderungen der Teilchentherapie mit Experimenten am Teilchenbeschleuniger untersucht. Ergebnisse: Es wurde ein Detektorsystem auf Basis von CZT Pixeldetektoren entwickelt und erprobt. Obwohl der Einsatz einer anwendungsspezifischen integrierten Schaltung zweckmäßig wäre, wurde dieser Ansatz zurückgewiesen, da kein verfügbarer Schaltkreis die Anforderungen erfüllte. Stattdessen wurde eine vielkanalige, kompakte und rauscharme analoge Verstärkerschaltung mit seriengefertigten integrierten Schaltkreisen aufgebaut. Letztendlich werden die 65 Informationskanäle eines Detektors digitalisiert, verarbeitet und visualisiert. Eine fortschrittliche digitale Signalverarbeitung überführt die traditionellen Ansätze der Nuklearelektronik in Algorithmen und digitale Filterstrukturen für einen FPGA. Es konnte gezeigt werden, dass die digitale Pulsverarbeitung in Bezug auf die charakteristischen Signale (u.a. variierende Anstiegszeiten, tiefenabhängige Energiemessung) eines CZT Pixeldetektors eine sehr gute Energieauflösung (~2% FWHM at 511 keV) sowie eine Zeitmessung im Bereich von einigen 10 ns ermöglicht. Weiterhin haben die experimentellen Ergebnisse gezeigt, dass der Dynamikbereich des Detektorsystems im Vergleich zum bestehenden Prototyp der Compton-Kamera deutlich verbessert werden konnte (~10 keV..7 MeV). Nach allem konnten auch Zählraten von >100 kcps in einem hochenergetischen Strahl mit dem CZT Pixeldetektor verarbeitet werden. Dies stellt aber lediglich eine Begrenzung des Detektors aufgrund seines Volumens, nicht jedoch der Elektronik, dar. Zudem wurde die Vielseitigkeit der digitalen Signalverarbeitung auch mit anderen Detektormaterialen (u.a. CeBr3) demonstriert. Mit Voraussicht auf einen hohen Datendurchsatz in einer verteilten Datenerfassung von mehreren Detektoren, wurde als Datenschnittstelle eine Gigabit Ethernet Verbindung implementiert. Schlussfolgerung: Um die Leistungsfähigkeit eines CZT Pixeldetektors vollständig auszunutzen, ist eine digitale Signalverarbeitung zwingend notwendig. Ein entscheidender Vorteil des digitalen Ansatzes ist die einfache Handhabbarkeit in einem vielkanaligen System. Mit der Digitalisierung wurde ein notwendiger Schritt getan, um die Komplexität einer Compton-Kamera beherrschbar zu machen. Weiterhin zeigt die Technologiebewertung, dass ein CZT Pixeldetektor den Anforderungen der Teilchentherapie für die Messung prompter Gammastrahlen stand hält. Der bisher eingesetzte Streifendetektor muss zugunsten einer gesteigerten Effizienz und verbesserter Energieauflösung durch den Pixeldetektor ersetzt werden. Mit der Integration des entwickelten digitalen Detektorsystems in eine Compton-Kamera muss abschließend geprüft werden, ob dieses Verfahren für die Reichweitenkontrolle in der Teilchentherapie anwendbar ist. Auch wenn sich herausstellt, dass ein anderes Verfahren unter klinischen Bedingungen praktikabler ist, so kann auch dieses Detektorsystem von der gezeigten Instrumentierung eines digitalen Signalverarbeitungssystems profitieren.

The increasing demand for energy efficient computing has endorsed the usage of Field-Programmable Gate Arrays to create hardware accelerators for large and complex codes. However, implementing such accelerators involve two complex decisions. The first one lies in deciding which code snippet is the best to create an accelerator, and the second one lies in how to implement the accelerator. When considering both decisions concomitantly, the problem becomes more complicated since the code snippet implementation affects the code snippet choice, creating a combined design space to be explored. As such, a fast design space exploration for the accelerators implementation is crucial to allow the exploration of different code snippets. However, such design space exploration suffers from several time-consuming tasks during the compilation and evaluation steps, making it not a viable option to the snippets exploration. In this work, we focus on the efficient implementation of pipelined hardware accelerators and present our contributions on speeding up the pipelines creation and their design space exploration. Towards loop pipelining, the proposed approaches achieve up to 100× speed-up when compared to the state-uf-the-art methods, leading to 164 hours saving in a full design space exploration with less than 1% impact in the final results quality. Towards design space exploration, the proposed methods achieve up to 9:5× speed-up, keeping less than 1% impact in the results quality. / A demanda crescente por computação energeticamente eficiente tem endossado o uso de Field- Programmable Gate Arrays para a criação de aceleradores de hardware para códigos grandes e complexos. Entretanto, a implementação de tais aceleradores envolve duas decisões complexas. O primeiro reside em decidir qual trecho de código é o melhor para se criar o acelerador, e o segundo reside em como implementar tal acelerador. Quando ambas decisões são consideradas concomitantemente, o problema se torna ainda mais complicado dado que a implementação do trecho de código afeta a seleção dos trechos de código, criando um espaço de projeto combinatorial a ser explorado. Dessa forma, uma exploração do espaço de projeto rápida para a implementação de aceleradores é crucial para habilitar a exploração de diferentes trechos de código. Contudo, tal exploração do espaço de projeto é impedida por várias tarefas que consumem tempo durante os passos de compilação a análise, o que faz da exploração de trechos de códigos inviável. Neste trabalho, focamos na implementação eficiente de aceleradores pipeline em hardware e apresentamos nossas contribuições para o aceleramento da criações de pipelines e de sua exploração do espaço de projeto. Referente à criação de pipelines, as abordagens propostas alcançam uma aceleração de até 100× quando comparadas às abordagens do estado-da-arte, levando à economia de 164 horas em uma exploração de espaço de projeto completa com menos de 1% de impacto na qualidade dos resultados. Referente à exploração do espaço de projeto, as abordagens propostas alcançam uma aceleração de até 9:5×, mantendo menos de 1% de impacto na qualidade dos resultados.

Les travaux présentés dans ce mémoire de thèse s'intéressent à la validation fonctionnelle de contrôleurs logiques par des techniques de test de conformité et de validation en boucle fermée. Le modèle de spécification est décrit dans le langage industriel Grafcet et le contrôleur logique est supposé être un automate programmable industriel (API) mono-tâche. Afin de contribuer à ces techniques de validation fonctionnelle, ces travaux présentent : - Une extension d'une méthode de formalisation du Grafcet par traduction sous la forme d'une machine de Mealy. Cette extension permet de produire un modèle formel de la spécification lorsque le Grafcet est implanté selon un mode d'interprétation sans recherche de stabilité, qui n'est pas préconisé dans la norme IEC 60848 mais largement utilisé dans les applications industrielles. - Une contribution au test de conformité par la définition d'un ensemble de relations de conformité basées sur l'observation de plusieurs cycles d'exécution pour chaque pas de test. - Une contribution à la validation en boucle fermée par la définition d'un critère de fin d'observation et par une technique d'identification en boite grise pour la construction et l'analyse du système en boucle fermée. / The results presented in this PhD thesis deal with functional validation of logic controllers using conformance test and closed-loop validation techniques. The specification model is written in the Grafcet language and the logic controller is assumed to be a Programmable Logic Controller (PLC). In order to contribute to these validation techniques, this thesis presents: - An axtension to a fomalization methods for Grafcet languages by translation to a Mealy machine. This extension generates a formal model of a Grafcet specification that is interpreted without search of stability. This mode of interpretation is not recommended by the standard IEC 60848 but is widely used in industrial applications. - A contribution to conformance test by a definition of a set of conformance relation based on the observation of several execution cycles for each test step. - A contribution to closed-loop validation by the definition of a termination criterion and by a new gray-box identification technique that is used for construction and analysis of the closed-loop system.

Ce mémoire s’inscrit dans le contexte général de la continuité de service des convertisseurs multiniveaux, lors de la défaillance d’un de leurs composants de puissance. Les structures concernées sont les topologies suivantes, largement utilisées dans les applications industrielles : Neutral Point Clamped (NPC) et Neutral Point Piloted (NPP) ou T-Type. Dans un premier temps, afin de limiter le taux de pannes du convertisseur, une commande contribuant à l’accroissement de la durée de vie des composants de puissance est tout d’abord proposée. Pour se faire, nous minimiserons sur chaque période le nombre de commutations des composants commandables à l’ouverture et à la fermeture. Cette idée a pour origine le fait qu’un convertisseur multiniveaux permet de générer le même niveau de tension de sortie à partir de plusieurs séquences de commutations différentes. Le principe de la commande proposée sera développé de manière générale, puis appliqué aux cas de structures type « Pont en H » à 5 niveaux, de type NPP (ou T-Type) et NPC. Ensuite, nous étudierons la continuité de service en mode nominal d’un convertisseur « Pont en H » à 5 niveaux, de type NPP (ou T-Type), suite à la défaillance en circuit ouvert d’un composant de puissance. Nous proposerons tout d’abord un diagnostic du défaut, constitué d’une première étape de détection, suivie d’une localisation précise du composant défaillant. Une topologie originale de convertisseur à tolérance de pannes permettra de garantir la continuité de service du système, en modifiant sa commande en adéquation avec le composant défaillant localisé. Des architectures électroniques numériques reconfigurables basées sur des composants FPGA (Field Programmable Gate Array) seront dédiées au diagnostic et à la reconfiguration de la commande ; elles permettront d’atteindre des performances temporelles élevées. L’ensemble des résultats présentés dans ce mémoire sera validé par modélisation/simulation, puis expérimentalement sur un banc de test / This thesis deals with continuity of service of multilevel power converters, during the failure of one of their power components. The studied converter topologies are the following, widely used in industrial applications: Neutral Point Clamped (NPC) and Neutral Point Piloted (NPP) or T-Type. First, to reduce the failure rate of the converter, an advanced control is proposed ; it increases the lifetime of the power components by minimizing the number of switchings over a period. This idea is based on the fact that a multilevel converter makes possible to generate the same output voltage level from several different switching sequences. The principle of the proposed control will be developed in a general way. Then, it is applied to the cases of 5-level "H-bridge" topologies, NPP (or T-Type) and NPC. Then, the continuity of service in nominal mode is studied for a 5 level "H-brige" NPP (or T-Type) converter, when an open circuit failure occurs on a power component. We first propose a fault diagnosis, consisting in a fault detection step, followed by the location of the faulty component. Then, an original fault-tolerant converter topology will ensure the continuity of service of the system, by modifying the control according to the localized faulty component. Reconfigurable digital electronic architectures based on Field Programmable Gate Array (FPGA) components will be dedicated to the diagnosis and the reconfiguration of the control; they will perform high temporal performances. All the results presented in this paper are validated by modeling and simulation. Then, they are experimentally validated on a test bench

by Chiu Wai Tak. / Thesis (M.B.A.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 54-55). / ABSTRACT --- p.iii / TABLE OF CONTENTS --- p.iv / LIST OF FIGURES AND TABLES --- p.vi / ACKNOWLEDGMENTS --- p.vii / CHAPTER / Chapter I. --- INTRODUCTION --- p.1 / The Microcontroller Market --- p.1 / About National Semiconductor Corporation --- p.3 / Project Objectives --- p.4 / Chapter II. --- METHODOLOGY --- p.7 / Market Research and Data Collection --- p.7 / Literature Review --- p.9 / Chapter III. --- MARKET ENVIRONMENT ANALYSIS --- p.11 / The OTP Microcontroller Market --- p.11 / Customer Profile --- p.16 / Competition Profile --- p.17 / National's Microcontroller Profile --- p.21 / SWOT Analysis --- p.24 / Chapter IV. --- MARKETING STRATEGY --- p.29 / Marketing Objective and Value Proposition --- p.29 / Product Strategy --- p.30 / Pricing Strategy --- p.32 / Distribution Strategy --- p.33 / Promotional Strategy --- p.35 / Chapter V. --- LIMITATIONS --- p.40 / About the Research --- p.40 / About the Marketing Plan --- p.40 / Chapter VI. --- CONCLUSION --- p.42 / Chapter APPENDIX I: --- TYPICAL MICROCONTROLLER APPLICATION --- p.44 / Chapter APPENDIX II: --- EXPERIENCE SURVEY PROCESS --- p.45 / Chapter APPENDIX III: --- REASONS FOR PROJECTS WON AND LOST --- p.46 / Chapter APPENDIX IV: --- BENEFITS OF COP8SA's FEATURES --- p.47 / Chapter APPENDIX V: --- COP8SA PRESS RELEASE --- p.48 / Chapter APPENDIX VI: --- GLOSSARY --- p.52 / BIBLIOGRAPHY --- p.54

The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs.

With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.

This work is a first step towards a long-term goal of understanding computations occurring in the brain and using those principles to make more efficient machines. The traditional computing paradigm calls for using digital supercomputers to simulate large scale brain-like neural networks resulting in large power consumption which limits scalability or model detail. For example, IBM's digital simulation of a cat brain with simplistic neurons and synapses consumes power equivalent to that of a thousand houses! Instead of digital methods, this work uses analog processing concepts to develop scalable, low-power silicon models of neurons which have been shown to be around ten thousand times more power efficient. This has been achieved by modeling the dynamical behavior of Hodgkin-Huxley (H-H) or Morris-Lecar type equations instead of modeling the exact equations themselves. In particular, the two silicon neuron designs described exhibit a Hopf and a saddle-node bifurcation. Conditions for the bifurcations allow the identification of correct biasing regimes for the neurons. Also, since the hardware neurons compute in real time, they can be used for dynamic clamp protocols in addition to computational experiments. To empower this analog implementation with the flexibility of a digital simulation, a family of field programmable analog array (FPAA) architectures have been developed in 0.35 um CMOS that provide reconfigurability in the network of neurons as well as tunability of individual neuron parameters. This programmability is obtained using floating-gate (FG) transistors. The neurons are organized in blocks called computational analog blocks (CAB) which are embedded in a programmable switch matrix. An unique feature of the architecture is that the switches, being FG elements, can be used also for computation leading to more than 50,000 analog parameters in 9 sq. mm. Several neural systems including central pattern generators and coincidence detectors are demonstrated. Also, a separate chip that is capable of implementing signal processing algorithms has been designed by modifying the CAB elements to include transconductors, multipliers etc. Several systems including an AM demodulator and a speech processor are presented. An important contribution of this work is developing an architecture for programming the FG elements over a wide dynamic range of currents. An adaptive logarithmic transimpedance amplifier is used for this purpose. This design provides a general solution for wide dynamic range current measurement with a low power dissipation and has been used in imaging chips too. A new generation of integrated circuits have also been designed that are 25 sq. mm in area and contain several new features including adaptive synapses and support for smart sensors. These designs and the previous ones should allow prototyping and rapid development of several neurally inspired systems and pave the path for the design of larger and more complex brain like adaptive neural networks.