International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / The ISM bands have opened up new opportunities for telemetry using spread-spectrum communications. A low-cost frequency-hopping radio is described here for the 900 MHz ISM band that can be programmed with a wide range of hop and data rates. The ‘C6201 DSP from TI is used to control the frequency and data rate of the TI TRF6900 transceiver chip using a custom interface of the 6201 EVM board to the serial I/O on the 6900 evaluation board.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive proposition for the low volume space market. Soft-core processors combine the power of programmable logic with the ease of use of a conventional processor to provide a highly customisable solution. However, the SRAM FPGAs used as implementation platform are especially susceptable to radiation induced single event upsets, due to the sensitivity of their configuration memory. To safely use these processors in a space environment requires the modification of the processor to safely mitigate these effects. This thesis presents the process followed to develop and test a fault tolerant implementation of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA. A thorough investigation was made into the available methods that can be used to mitigate single event upsets, in order to identify the most suitable ones. Guidelines for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A single event upset simulator was designed and constructed to compare the different techniques. It mimics SEUs by injecting errors into the configuration memory of an FPGA. The results of error injection were used to develop a PicoBlaze implementation with limited overhead, while it still offers a high degree of error mitigation. Three different designs were tested by proton irradiation to verify the protection afforded by the mitigation techniques. It was found that protected designs were more robust. The cross-section of the FPGA was also determined, which can be used with the SEU simulator to predict the dynamic cross-section of designs. The work contained in this thesis demonstrates the use of open-source intellectual property with commercial-off-the-shelf components to develop a robust component for use in the miniature spacecraft market.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

Master of Science / Department of Electrical Engineering / Dwight Day / Power consumption has become a large concern in many systems including portable electronics and supercomputers. Creating efficient hardware that can do more computation with less power is highly desirable. This project proposes a possible avenue to complete this goal by hardware accelerating a conjugate gradient solve using a Field Programmable Gate Array (FPGA). This method uses three basic operations frequently: dot product, weighted vector addition, and sparse matrix vector multiply. Each operation was accelerated on the FPGA. A power monitor was also implemented to measure the power consumption of the FPGA during each operation with several different implementations. Results showed that a decrease in time can be achieved with the dot product being hardware accelerated in relation to a software only approach. However, the more memory intensive operations were slowed using the current architecture for hardware acceleration.

The performance of distributed key-value stores is usually dependent on its underlying network, and have potential to improve read/write latencies by improving upon the per- formance of the network communication. We explore the potential performance increase by designing an experimental in-network cache based on NetCache in the switch data plane for the distributed key-value store DXRAM, and placing it on a programmable switch that connects the peers in a DXRAM storage cluster. To accomodate DXRAM which uses TCP for its transport protocol, we also design a TCP flow state translator for the cache and implement an experimental version of this cache design. Benchmark runs with the cache show that best-case item read latency for DXRAM is reduced to approximately half and prove the potential performance gain that can be expected once a proper cache is designed and implemented.

Orientador: Eduardo Martins Morgado / Banca: Maria Crsitina Gobbi / Banca: Adriana Bertoldi Carreto de Castro / Resumo: Em um mundo onde as pessoas estão cada vez mais conectadas, chega o momento em que os objetos também passam a fazer parte da rede de compartilhamentos. Com a possibilidade de conexão de equipamentos por meio de hardware com capacidade de telecomunicação e de processamento para executar moderno software embarcado, é cada vez mais acessível tecnológica e economicamente o desenvolvimento de novos produtos conectados. Esta pesquisa discute parte da evolução da Internet das Coisas (IoT) e de algumas de suas aplicações, propondo a criação de um dispositivo conectado a esta rede. Sendo o objeto deste trabalho a IoT, dentro da grande gama de dispositivos que poderiam ser criados, foi colocado foco em desenvolver uma aplicação para coleta e leitura de dados climáticos. Como metodologia, a partir da pesquisa bibliográfica, será desenvolvido um relatório de pesquisa com construção de um protótipo. Atualmente o mercado dispõe de produtos de alto custo para leitura de dados climáticos, quase sempre importados ou desenvolvidos por empresas multinacionais, havendo pouca tecnologia nacional disponível para consumidores finais. Reserva-se esta a grandes centros de pesquisa de referência nacional. Foi desenvolvido um dispositivo para adequar-se aos fins propostos no trabalho, para responder à questão seria possível desenvolver um dispositivo para coleta e leitura de dados climáticos. O objeto deste trabalho é a Internet das Coisas. O objetivo geral foi verificar as características para desenvo... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: In a world where people are increasingly connected, comes the time when objects also become part of the share's network. With the possibility of connecting hardware by means of hardware with the capability of communication and processing for the execution of modern embedded software, the development of new connected products is increasingly accessible and economically. This research discusses part of the evolution of the Internet of Things (IoT) and some of its applications, proposing a creation of a device connected to this network. Being the object of this work an IoT, within the wide range of devices that are being inserted, were putted in focus an application for the data collection and reading of climatic data. As a methodology, from the bibliographic research, a research report will be developed with the construction of a prototype. Now a days, the market for high-priced climate data products, almost always imported or by multinational companies, has national technology available to end consumers. Reserves to major research centers of national reference. A device was developed to fit the purposes proposed in the work, to answer the question it would be possible to develop a device for collecting and reading climatic data. The object of this work is the Internet of Things. The general objective was to verify the characteristics for the development of an IoT device to perform the reading of climatic data. The specific objectives were: to define ways to collect climate dat... (Complete abstract click electronic access below) / Mestre

Gegenstand der Arbeit stellt eine erstmalig unternommene, architekturübergreifende Studie über feldprogrammierbare Logikbausteine zur Implementierung synchroner Schaltkreise dar. Zunächst wird ein Modell für allgemeine feldprogrammiebare Architekturen basierend auf periodischen Graphen definiert. Schließlich werden Bewertungsmaße für Architekturen und Schaltkreislayouts angegeben zur Charakterisierung struktureller Eigenschaften hinsichtlich des Verhaltens in Chipflächenverbrauch und Signalverzögerung. Ferner wird ein generisches Layout-Werkzeug entwickelt, das für beliebige Architekturen und Schaltkreise Implementierungen berechnen und bewerten kann. Abschließend werden neun ressourcenminimalistische Architekturen mit Maschen- und mit Inselstruktur einander gegenübergestellt. / This work presents a first architecture-spreading study on field-programmable logical devices leaving the beaten tracks of commercial architecture improvements. After a formal model for general field-programmable architectures based on periodic graphs has been given, some feasible evaluation metrics for architectures and circuit layouts are defined characterizing structural properties of architectures in respect of chip area usage and performance. Then, a generic layout tool is developped working on arbitrary architecures and circuits. Finally, nine resource minimal mesh- and island-style architectures are compared.

Um sistema que realiza a detecção de movimento procura, numa seqüência de imagens, sinais que confirmem a existência de movimentação no ambiente monitorado. Uma vez realizada a detecção do movimento, pode-se realizar o rastreamento (tracking) do objeto na cena em questão. A detecção e o rastreamento de objetos, em tempo real, são técnicas que estão despertando grande interesse por parte de pesquisadores e empresas pois, estas técnicas, podem ser utilizadas em diversas áreas que se estendem desde a engenharia e computação até áreas como a geologia e medicina. Sendo assim, seguindo-se a idéia básica de detecção e rastreamento, encontram-se diversas aplicações para estas técnicas como: sistemas de vigilância, análise de movimentos humanos, sistemas de detecção e rastreamento de pedestres ou veículos, dentre outras. Neste trabalho é mostrado um sistema que foi desenvolvido para armazenamento de imagens em tons de cinza de uma seqüência de vídeo e um posterior processamento dessas imagens para detecção de características que indiquem movimento. O processamento se resume em integrar o sinal de vídeo, que está armazenado nas memórias, nas direções horizontal e vertical gerando os histogramas de intensidade horizontal e vertical. Comparando os histogramas de quadros diferentes da seqüência de vídeo será possível detectar a presença de movimento e a região da imagem onde este ocorreu. Devido à necessidade de um processamento rápido das imagens e no interesse de produzir um sistema dedicado com hardware reduzido, utilizou-se de dispositivos de lógica programável complexa (CPLDs). / A system that performs movement detection in a sequence of images looks for signs that confirm the occurrence of the movement in the controlled environment. Once the movement of the object is detected it is possible to perform the tracking of the object. Real time object detection and tracking techniques are of great interests to researchers and industries because these techniques can be used in several areas going from engineering and computing to geology and medicine. There is a wide field of applications of detection and tracking techniques, such as: surveillance systems, human movement analysis, pedestrians or vehicle detection. This work presents an implementation able to store a gray level image from a video sequence and from these images detect in real time a object movement in the scene. The detection will be performed integrating an image from the video sequence in the horizontal and vertical directions in order to obtain the intensities histograms in these directions. Comparing the histograms with those of a different frame of the video sequence it will be possible to detect the presence of movement and locate where in the image the movement occurs. Due to real time digital image processing requirements and in order to produce a reduce dedicated hardware, complex programmable logic devices (CPLDs) were used.

A morfologia matemática é o estudo da forma utilizando as ferramentas da teoria de conjuntos e representa uma área extremamente importante em análise de imagens. Suas operações básicas são a dilatação e a erosão, e através destas é possível realizar outras operações mais complexas. A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas destas aplicações requerem processamento em tempo real, e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. A análise de imagens em baixo nível geralmente envolve computações repetidas sobre estruturas grandes de dados. Assim, o paralelismo parece ser um atributo necessário de um sistema de hardware capaz de executar eficientemente estas tarefas. As ferramentas da morfologia matemática são bem adequadas à implementação em arquiteturas pipeline. A necessidade de sistemas capazes de realizar o processamento de imagens digitais em tempo real, com o menor custo e tempo de desenvolvimento, tem sido suprida pela tecnologia de dispositivos de lógica programável complexa. Assim, neste trabalho foi projetada e implementada uma arquitetura pipeline dedicada para dilatação e erosão de imagens binárias em tempo real utilizando dispositivos lógicos programáveis de alta capacidade. Esta arquitetura é capaz de processar imagens binárias de 512 x 512 pixels. Os estágios desta arquitetura são flexíveis, permitindo a reprogramação da forma e do tamanho dos elementos estruturantes utilizados nas operações morfológicas. A arquitetura desenvolvida apresentou um desempenho satisfatório, demonstrando ser uma alternativa viável e eficiente. / Mathematical morphology is a very important image analysis area that uses set theory tools to study shapes. The basic operations in mathematical morphology are dilation and erosion, these can be used for more complex operations. Mathematical morphology has powerful tools for low level image processing and has been used in a wide range of applications such as robotic vision, visual inspection, medicine and texture analysis. Low level image processing requires repetitive processing over large data structures, dedicated parallel computing hardware is often used. Complex field programmable logic devices (CPLDs) have increasingly been used for the fast development of real time image processing systems. In this work we present a pipeline architecture for real time erosion and dilation operations, the architecture was developed using high density programmable logic devices. The developed architecture can process 512 x 512 pixels binary images, and has flexible stages that can be reprogrammed according to the shape and size of the structuring elements used in the morphological operations. Tests performed using the architecture demonstrated its good performance and that it is a good and efficient alternative for dedicated morphological image processing operations.