Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing specific operations much like math and image processing coprocessors, or execute operations upon multiple processors in a parallel fashion. Due to the increase in developing applications for the manipulation of logic functions, an interest in the logic machine has arisen. Many applications such as logic optimization, simulation, pattern recognition and image processing can be better implemented with a logic machine. This thesis proposes the design, hardware realization, and testing of the iterative logic unit (ILU) of the Cube Calculus Machine II (CCM2). The CCM2 is a general purpose computer with an architecture that emphasizes a data path designed to execute operations of cube calculus, a popular algebraic model used in the minimization of Boolean functions. The ILU is an iterative logic array of cells (ITs) using internal distributed control, enabling the execution of basic cube operations, while the Control Unit (CU) handles global signals from the host computer. The ILU of the CCM2 has been realized in hardware using Xilinx Logic Cell Arrays (LCAs). FPGAs offer the logic density and versatility of gate arrays, with the off-the shelf availability and time-to-market advantages of standard user-programmable devices. These devices can be reconfigured, allowing multiple revisions and future design generations to accommodate the same device, thus saving design and production costs, an ideal solution to the resource and financial problems plaguing the University environment.

The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.

This thesis presents a new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs. We represent the netlist as the binary tree with decision variables associated with each node of the tree. The functionality of the tree nodes is chosen based on the target FPGA architecture. The proposed tree restructuring algorithms preserve local connectivity and allow direct mapping of the trees to the cellular array, thus eliminating the traditional routing phase. Also, predictability of the signal delays is a very important advantage of the developed approach. The developed bus-assignment algorithm efficiently utilizes the medium distance routing resources (buses). The method is general and can be used for any Fine Grain CA-type FPGA. To demonstrate our techniques, ATMEL 6000 series FPGA was used as a target architecture. The area and delay comparison between our methods and commercial tools is presented using a set of MCNC benchmarks. Final layouts of the implemented designs are included. Results show that the proposed techniques outperform the available commercial tools for ATMEL 6000 FPGAs, both in area and delay optimization.

Unmanned vehicles, both ground and aerial, have become prevalent in recent years. The research community has different needs than the industrial community when designing a finalized unmanned system since the vehicle, the sensors and the control design are dynamic and change frequently as new ideas are developed and implemented. Current autopilot hardware, which is available as on-the-market products and proposed in research, is sufficient for unmanned systems design. However, this equipment falls short of being able to accommodate the needs of those in the research community who must be able to quickly implement new ideas on a flexible platform. The contribution of this research is the realization of a hardware platform, which provides for rapid implementation of newly developed theory. Rapid implementation is gained by providing for software development from within the Simulink environment and utilizing previously unrealized flexibility in sensor selection. In addition to the development of the hardware platform, research was performed within Simulink's System Generator environment in order to complement the hardware. The software produced consists of a user template that integrates to the selected hardware. The template creates a user friendly environment, which provides the end user the capability to develop software algorithms from within the Simulink environment. This capability facilitates the final step of full hardware implementation. The major novelty of the research was the overall FPGA based autopilot design. The approach provided flexibility, functionality and generality. The approach is also suitable for and applicable to the design of multiple platforms. This research yielded a first time approach to the development of an unmanned systems autopilot platform by utilizing: -Development of programmable voltage level digital Input/Output (I/O), ports, -Utilization of Field Programmable Analog Arrays (FPAA), -Hardware capabilities to allow for integration with full computer systems, -A full Field Programmable Gate Array (FPGA), implementation, -Full integration of the hardware within Simulink's System Generator Toolbox

Thesis (M.S. in computer engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 82-83).

In modern point to point microwave radio systems used to backhaul cellular voice and data traffic, quadrature amplitude modulation (QAM) is the norm. These systems require a highly linear power amplifier which is expensive and has relatively low power efficiency. Recently, continuous phase modulation (CPM) has been deployed in this market. The CPM transmitted waveform has a constant envelope and so a non-linear RF power amplifier can be used. This significantly reduces cost and improves power efficiency. Two important disadvantages of CPM are receiver complexity and inferior spectral efficiency compared to QAM. This thesis demonstrates a 50% spectral efficiency improvement over an existing CPM configuration without loss of detection efficiency. This is achieved by moving to coherent demodulation and extending the duration of the CPM phase pulse to 3 symbol periods. This new CPM configuration of h=1/4, M=4, L=3, is evaluated against ETSI requirements for a 28 MHz channel carrying 24 E1 circuits. Simulation of the receiver floating point model demonstrates all requirements are met. The detection efficiency requirement is exceeded by 4.7 dB. Carrier recovery, phase and timing synchronisation are assumed to be ideal. The 50% increased symbol rate, coherent reception and a longer smoother phase pulse, conspire to increase receiver complexity substantially. The Viterbi algorithm is used to perform maximum-likelihood detection resulting in a 128 state trellis. This application has a stringent cost requirement that limits the implementation target to a Field Programmable Gate Array (FPGA) costing less than US$30. To demonstrate this demanding cost target is met, the two most computationally expensive receiver functions, the branch metric unit and path metric processing unit, are implemented in VHDL and targeted to a Xilinx Spartan 3A-DSP 1800 FPGA. The implementation uses 67% of the available logic resources, thus meeting the cost requirement. The branch metric unit is implemented using a distributed arithmetic technique that performs the equivalent of 27.6 giga-multiplies/s, consuming only 23% of the available FPGA logic cells. This is very efficient compared to a conventional approach using all the FPGA’s embedded multipliers which combined can only achieve 21 giga-multiplies/s. The Viterbi path metric processing unit is implemented using a more conventional state-parallel architecture. To reduce state metric routing complexity, states are grouped into radix-4 units comprising dual add-compare-select (ACS) units. By utilising a spare cycle in the deep ACS pipeline, each ACS unit processes two output state metrics, thus halving the number of ACS units required. This implementation uses 44% of the available FPGA resources and meets timing at 204.5 MHz, exceeding the throughput requirement of 54 Mbit/s.

L'optimisation de la synthèse logique de circuits dépend de la structure matérielle cible pour les circuits combinatoires (logique aléatoire, réseaux prédiffusés, PLA...) ainsi que de l'architecture choisie par le concepteur pour les circuits plus complexes (contrôleur). On propose un système de synthèse flexible à base de règles (système ASYL). Ces règles traduisent les critères d'optimisation des structures cibles ainsi que les choix de conception. L'illustration pratique concerne essentiellement la synthèse des fonctions booléennes sur PLA et la synthèse de contrôleur

Récemment le domaine du traitement de l'image, de la vidéo, et l'audio a connu plusieurs évolutions importantes au niveau des algorithmes et des architectures. L'une de ces évolutions est l'apparition du nouveau standard ISO/IEC de compression d'image JPEG2000 qui succède à JPEG. Ce nouveau standard présente de nombreuses fonctionnalités et caractéristiques qui lui permettent d'être adapté à une large panoplie d'applications. Mais ces caractéristiques se sont accompagnées d'une complexité algorithmique beaucoup plus élevée que JPEG et qui le rend très difficile à optimiser pour certaines implémentations ayant des contraintes très sévères en terme de surface, de temps d'exécution ou de consommation d'énergie ou de l'ensemble de ces contraintes. L'une des étapes clé dans le processus de compression JPEG2000 est le codeur entropique qui constitue à lui seul environ 70% du temps de traitement global pour la compression d'une image. Il est donc essentiel d'analyser les possibilités d'optimisation d'implémentations de JPEG2000. Les circuits FPGA sont aujourd'hui les principaux circuits reconfigurables disponibles sur le marché. S'ils ont longtemps été utilisés uniquement pour le prototypage des ASIC, ils sont aujourd'hui en mesure de fournir une solution efficace à la réalisation matérielle d'applications dans de nombreux domaines. Vu le progrès que connaît l'industrie des composants FPGA du point de vue capacité d'intégration et fréquence de fonctionnement, les architectures reconfigurables constituent aujourd'hui une solution efficace et compétitive pour répondre aussi bien aux besoins du prototypage qu'à ceux des implémentations matérielles. Dans ce travail nous proposons une démarche pour l'étude des possibilités d'implémentations de JPEG2000. Cette étude a débuté avec l'évaluation d'implémentations logicielles sur plateformes commerciales. Des optimisations logicielles ont été ajoutées en utilisant des librairies SIMD spécialisées exploitant du parallélisme à grain fin. Suite à cette première étude on a réalisé une implémentation matérielle d'un bi codeur entropique sur FPGA qui a servi comme coprocesseur pour deux plateformes distinctes l'une étant une machine hôte et l'autre un système industriel embarqué. Suite à cette étape nous avons fait évoluer l'implémentation en passant à une deuxième approche qui est l'approche système sur puce programmable. Dans cette dernière partie nous avons effectué le partitionnement matériel/logiciel du codeur entropique sur FPGA, puis une implémentation multi codeur a été réalisée sur FPGA et utilisée comme coprocesseur sur puce pour la création d'un système sur puce programmable. Ces différents travaux ont permis de couvrir une partie de l'espace des applications que JPEG2000 peut cibler. En même temps ces implémentations donnent une vue globale sur les possibilités des implémentations de JPEG2000 ainsi que leurs limites. De plus cette étude représente un moyen pour décider de l'adéquation architecture application de JPEG2000.

No description available.

<p>Denna rapport omfattar ett 15 poängs (22,5 högskolepoäng) examensarbete vid Karlstads universitet. Arbetet har utförts på plats hos BAE Systems Bofors i Karlskoga. Företaget ville kunna styra en radiostyrd leksaksstridsvagn med en laserpekare. En kamera ansluten till en digital signalprocessor (DSP) skulle kunna detektera var en laserpunkt befinner sig och styra stridsvagnen mot den.</p><p>Ett styrgränssnitt mellan DSP:n och leksaksstridsvagnen konstruerades och byggdes med hjälp av en programmerbar logisk krets. Leksaksstridsvagnens interna signalsystem analyserades. En manchesterkodad signal i form av ett 32-bitars seriellt kodord hittades, vilket ursprungligen kom från radiostyrningen. Ett styrgränssnitt konstruerades kring en CPLD (Complex Programmable Logic Device) vilken programmerades med VHDL (Very high speed integrated Hardware Description Language) som återskapar den Manchesterkodade styrsignalen.</p><p>Gränssnittet ansluter till DSP:n som kontrollerar stridsvagnens styrning och övriga funktioner till fullo. Kommunikationen mellan styrgränssnittet och DSP:n sker via ett parallellgränssnitt som är 16-bitar brett. 13 bitar är datasignaler och övriga tre är ”styrbitar” som konfigurerar gränssnittet. En applikation integrerades i projektet för att demonstrera styrgränssnittets funktion. DSP:n tolkar var en laserpunkt befinner sig inom ett kameraområde och skickar motsvarande styrsignaler till leksaksstridsvagnen.</p> / <p>This report consists of a 15 points (22.5 ECTS) Exam Degree project at Karlstad University. The work was done on location at BAE Systems Bofors AB in Karlskoga. The company wanted to control a radio controlled toy tank from a digital signal processor (DSP). A camera connected to the DSP locates the laser point and steers the toy tank towards it.</p><p>An interface using a programmable logic device was constructed that connects the DSP to the toy tank. The internal signals in the toy tank was analyzed and a Manchester coded signal in form of a 32-bit serial code word was detected. The code word originated from the radio controller. The control interface was built around a CPLD (Complex Programmable Logic Device) which was programmed in VHDL (Very high speed integrated Hardware Description Language). The control interface recreates the signal controlling the toy tank.</p><p>The interface connects the toy tank to the DSP which controls the toy tank and it’s functions to the full extent. Communication between the interface and the DSP is done via a 16 bit parallel connection. 13 of the bits are data bits and the remaining 3 are control bits that are used to set up the interface. An application was integrated in the project where the DSP is detecting a laser point. Corresponding signals to the laser points position where sent to the control interface to demonstrate the function of the interface.</p>