Les expectatives dels usuaris en relació a la quantitat i qualitat del serveis de xarxa estan creixent ràpidament. En canvi, desenvolupar e implantar nous serveis de xarxa (serveis que operen a nivell de xarxa) seguint el procés d'estandardització és massa lent i no pot satisfà les expectatives.Les xarxes actives i programables van ser proposades per acomodar la ràpida evolució de noves tecnologies i accelerar la implantació de serveis sofisticats. Les xarxes actives permeten que tercers (usuaris finals, operadors i proveïdors de servei) introdueixin serveis específics per aplicacions (en forma de codi) dins la xarxa. D'aquesta manera, les aplicacions poden fer servir aquests serveis per obtenir el suport necessari de la xarxa en termes de comportament per exemple.Tanmateix, les tecnologies de xarxes actives i programables introdueixen una complexitat addicional als elements de xarxa que ha de ser tractada pel sistema de gestió. Alguns exemples d'aquesta complexitat addicional són la necessitat de suportar nous serveis introduïts dinàmicament a la xarxa o la gestió de xarxes actives virtuals. Aquestes xarxes poden ser creades dins una infrastructura de xarxa programable per satisfer les creixents necessitats de control i particularització que els clients imposen a les xarxes. A més, la probable implantació progressiva de les xarxes actives i programables dins les xarxes IP actuals afegeix un altre requisit important al pla de gestió: aquest ha de ser capaç de suportar tecnologies de xarxa heterogènies (passives, actives i programables).La solució proposada en aquesta tesi millora els sistemes de gestió basats en polítiques amb conceptes de les tecnologies de xarxes actives i programables per satisfer tots els requisits abans esmentats; assolint, d'aquesta manera, una solució sòlida per la gestió de xarxes actives i programables.Finalment, l'arquitectura per la gestió de xarxes actives basada en polítiques (MANBoP) que proposem ha estat dissenyada per poder ser instanciada a qualsevol nivell de gestió (xarxa, sub-xarxa o element). A més, diferents instàncies es poden agrupar fàcilment per crear una infrastructura de gestió. Per exemple, una instància MANBoP de nivell de xarxa pot treballar sobre instàncies de nivell de element, o vàries instàncies de nivell de sub-xarxa poden ser creades per treballar en paral·lel, cadascuna gestionant una regió geogràfica de la xarxa diferent. L'objectiu d'aquest atribut de l'arquitectura és facilitar la tasca de creació d'una infrastructura de gestió. D'aquesta manera, els operadors de xarxa poden crear la infrastructura de gestió que més els convingui segons els seus objectius de negoci i reduir així els costs de gestió. / -RESUMENLas expectativas de los usuarios en relación con la cantidad y calidad de los servicios de red están creciendo rápidamente. En cambio, desarrollar e implantar nuevos servicios de red (servicios que operan al nivel de red) siguiendo los procesos de estandarización es demasiado lento y no colma las expectativas.Las redes activas y programables fueron propuestas para acomodar la rápida evolución de las nuevas tecnologías y acelerar la implantación de nuevos servicios más sofisticados. Las redes activas permiten que terceros (usuarios finales, operadores o proveedores de servicio) introduzcan servicios específicos para aplicaciones (en forma de código) dentro de la red. De esta forma, las aplicaciones pueden utilizar estos servicios para obtener el soporta que necesitan de la red en términos, por ejemplo, de comportamiento.Sin embargo, las tecnologías de redes activas y programables introducen una complejidad adicional en los elementos de red que debe ser tratada por el sistema de gestión. Algunos ejemplos de esta complejidad adicional son la necesidad de soportar nuevos servicios introducidos dinámicamente en la red o la gestión de redes activas virtuales. Éstas pueden ser creadas dentro de una infraestructura de red programable para satisfacer las necesidades crecientes de control y particularización que los clientes imponen sobre las redes. Además, la probable progresiva implantación de la redes activas y programables en la redes IP actuales añade otro importante requisito al plano de gestión: éste tiene que ser capaz de soportar tecnologías de red heterogéneas (pasivas, activas y programables).La solución propuesta en esta tesis mejora los sistemas de gestión basados en políticas con conceptos de las tecnologías de redes activas y programables para satisfacer todos los requisitos enumerados anteriormente, consiguiendo, de esta forma, una solución sólida para la gestión de redes activas y programables.Finalmente, la arquitectura de gestión de redes activas basada en políticas (MANBoP) que proponemos ha sido diseñada para poder ser instanciada en cualquier nivel de gestión (red, sub-red o elemento). Además, diferentes instancias pueden ser agrupadas fácilmente para crear una infraestructura de gestión. Por ejemplo, una instancia MANBoP de nivel de red puede trabajar sobre instancias de nivel de elemento, o varias instancias de nivel de sub-red pueden ser creadas para trabajar en paralelo sobre diferentes regiones geográficas de la red. El objetivo de esta característica de la arquitectura es facilitar la creación de una infraestructura de gestión para que los operadores de red puedan crear la que más les convenga según sus objetivos de negocio, reduciendo así los costes de gestión. / User expectations of the range and quality of network services are growing rapidly. However, developing and deploying new network services (i.e. services that operate on the network layer), through best practice and standardization, is too slow and cannot match the steps of expectations. Active and programmable networks were proposed to accommodate the rapid evolution of new technologies and accelerate the deployment of new sophisticated services. Active networks (AN) enable third parties (end users, operators, and service providers) to inject application-specific services (in the form of code) into the network. Applications are thus able to utilize these services to obtain required network support in terms of, e.g. performance; that is, applications are now becoming network-aware. Nonetheless, active and programmable networking technologies introduce additional complexity in network elements that must be handled by the management architecture. Examples of this additional complexity are the need of coping with new services dynamically introduced in the network, or the management of virtual active networks (VANs). VANs might be created over a programmable network infrastructure to satisfy increasing requirements for the control and customization of resources that customers impose on networks. Furthermore, the likely progressive deployment of active and programmable routers in today's IP networks introduces another important requirement in the management plane; that is, it has to be able to cope with heterogeneous network technologies, i.e., passive, active and programmable.The solution proposed in this thesis enhances a policy-based management system with active networking technology concepts to fulfill the above-mentioned requirements, thus achieving a sound solution for the management of active and programmable networks.In addition, the Management of Active Networks Based on Policies (MANBoP) framework proposed is designed to be instantiated at any management level (i.e. network, sub-network or element). Moreover, different instances can be easily set up jointly to create a management infrastructure, e.g., a network-level MANBoP instance can be set up over element-level instances, or several subnetwork-level instances can work in parallel each one managing a different geographical region of the network, etc. The aim of this framework property is to ease the management infrastructure creation task, thus allowing network operators to adapt the management infrastructure to their business needs, resulting in a reduction of management costs.

Abstract The development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those operations demanding stringent security levels but also many daily use consumer applications request the existence of computational platforms in charge of recognizing the identity of one individual based on the analysis of his/her physiological and/or behavioural characteristics. The state of the art points out two main open problems in the implementation of such applications: on the one hand, the needed reliability improvement in terms of recognition accuracy, overall security and real-time performances; and on the other hand, the cost reduction of those physical platforms in charge of the processing. This work aims at finding the proper system architecture able to address those limitations of current personal recognition applications. Embedded system solutions based on hardware-software co-design techniques and programmable (and run-time reconfigurable) logic devices under FPGAs or SOPCs is proven to be an efficient alternative to those existing multiprocessor systems based on HPCs, GPUs or PC platforms in the development of that kind of high-performance applications at low cost / El desenvolupament de sistemes automàtics de reconeixement personal basats en tècniques biomètriques esdevé una realitat en l’era tecnològica actual. No només aquelles operacions que exigeixen un elevat nivell de seguretat sinó també moltes aplicacions quotidianes demanen l’existència de plataformes computacionals encarregades de reconèixer la identitat d’un individu a partir de l’anàlisi de les seves característiques fisiològiques i/o comportamentals. L’estat de l’art de la tècnica identifica dues limitacions importants en la implementació d’aquest tipus d’aplicacions: per una banda, és necessària la millora de la fiabilitat d’aquests sistemes en termes de precisió en el procés de reconeixement personal, seguretat i execució en temps real; i per altra banda, és necessari reduir notablement el cost dels sistemes electrònics encarregats del processat biomètric. Aquest treball té per objectiu la cerca de l’arquitectura adequada a nivell de sistema que permeti fer front a les limitacions de les aplicacions de reconeixement personal actuals. Es demostra que la proposta de sistemes empotrats basats en tècniques de codisseny hardware-software i dispositius lògics programables (i reconfigurables en temps d’execució) sobre FPGAs o SOPCs resulta ser una alternativa eficient en front d’aquells sistemes multiprocessadors existents basats en HPCs, GPUs o plataformes PC per al desenvolupament d’aquests tipus d’aplicacions que requereixen un alt nivell de prestacions a baix cost. / El desarrollo de sistemas automáticos de reconocimiento personal basados en técnicas biométricas se ha convertido en una realidad en la era tecnológica actual. No tan solo aquellas operaciones que requieren un alto nivel de seguridad sino también muchas otras aplicaciones cotidianas exigen la existencia de plataformas computacionales encargadas de verificar la identidad de un individuo a partir del análisis de sus características fisiológicas y/o comportamentales. El estado del arte de la técnica identifica dos limitaciones importantes en la implementación de este tipo de aplicaciones: por un lado, es necesario mejorar la fiabilidad que presentan estos sistemas en términos de precisión en el proceso de reconocimiento personal, seguridad y ejecución en tiempo real; y por otro lado, es necesario reducir notablemente el coste de los sistemas electrónicos encargados de dicho procesado biométrico. Este trabajo tiene por objetivo la búsqueda de aquella arquitectura adecuada a nivel de sistema que permita hacer frente a las limitaciones de los sistemas de reconocimiento personal actuales. Se demuestra que la propuesta basada en sistemas embebidos implementados mediante técnicas de codiseño hardware-software y dispositivos lógicos programables (y reconfigurables en tiempo de ejecución) sobre FPGAs o SOPCs resulta ser una alternativa eficiente frente a aquellos sistemas multiprocesador actuales basados en HPCs, GPUs o plataformas PC en el ámbito del desarrollo de aplicaciones que demandan un alto nivel de prestaciones a bajo coste

Soft computing techniques are generally well-suited for vehicular control systems that are usually modeled by highly nonlinear differential equations and working in unstructured environment. To demonstrate their applicability, two intelligent controllers based upon fuzzy logic theories and neural network paradigms are designed for performing a wall-following task and an autonomous parking task. Based on performance and flexibility considerations, the two controllers are implemented onto a reconfigurable hardware platform, namely a Field Programmable Gate Array (FPGA). As the number of comparative studies of these two embedded controllers designed for the same application is limited in the literature, one of the main goals of this research work has been to evaluate and compare the two controllers in terms of hardware resource requirements, operational speeds and trajectory tracking errors in following different pre-defined trajectories. The main advantages and disadvantages of each of the controllers are presented and discussed in details. Challenging issues for implementation of the controllers on the FPGA platform are also highlighted. As the two controllers exhibit benefits and drawbacks under different circumstances, this research suggests as well a hybrid controller scheme as an attempt to integrate the benefits of both control units. To evaluate its performance, the hybrid controller is tested on the same pre-defined trajectories and the corresponding results are compared to that of the fuzzy logic and the neural network based controllers. For further demonstration of the capabilities of the wall-following controllers in other applications, the fuzzy logic and the neural network controllers are used in a parallel parking system. We see this work to be a stepping stone for further research work aiming at real world implementation of the controllers on Application Specified Integrated Circuit (ASIC) type of environment.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

No description available.

Reconfigurable devices are the mainstream in today’s system on chip solutions. Reconfigurable devices have the advantages of reduced cost over their equivalent custom design, quick time to market and the ability to reconfigure the design at will and ease. One such reconfigurable device is an FPGA. In this industrial thesis, the design and implementation of a control process interface using ECP2M FPGA and PCIe communication is accomplished. This control process interface is designed and implemented for a 3-D plotter system called LSC11. In this thesis, the FPGA unit implemented drives the plotter device based on specific timing requirements charted by the customer. The FPGA unit is interfaced to a Host CPU in this thesis (through PCIe communication) for controlling the LSC11 system using a custom software. All the peripherals required for the LSC11 system such as the ADC, DAC, Quadrature decoder and the PWM unit are also implemented as part of this thesis. This thesis also implements an efficient methodology to send all the inputs of the LSC11 system to the Host CPU without the necessity for issuing any cyclic read commands on the Host CPU. The RTL design is synthesised in FPGA and the system is verified for correctness and accuracy. The LSC11 system design consumed 79% of the total FPGA resources and the maximum clock frequency achieved was 130 Mhz. This thesis has been carried out at Abaxor Engineering GmbH, Germany. It is demonstrated in this thesis how FPGA aids in quick designing and implementation of system on chip solutions with PCIe communication.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs; in this work, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The LUT functionality is modified to incorporate the guards and reduce toggle rates. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering gating inputs using "non-inverting paths" and trimming inputs using "partial non-inverting paths" in the circuit's AND-Inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on average, and can reduce power consumption in the FPGA interconnect by 29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster and ten LUTs to a cluster produced the best power reduction results. We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged to insert high quality guards with minimal impact on routing. Experimental results show that post-packing and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical path delay and routability of the circuit.

This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.

In recent years, due to advances in semiconductor technology and mature integrated circuit design, complex signal processing equipment is beginning to be replaced by the integrated circuit. This paper presents an integrated circuit programmable frequency generator for open-loop resonator application and its evaluation. It can eventually replace the conventional discrete component system and be used to find the resonance frequency shift for the readout of micro-balances or similar devices. The oscillator provides an analog tuning input to set the coarse center frequency and bit resolution, and uses a digital input to control the frequency sweep. Calculating the resonance frequency difference between the active balance and a passive reference can mitigate some environmental effects on the resonator (e.g. temperature). The generator circuit is designed using Synopsys¡¦ HSPICE and Cadence's Spectre to perform circuit simulation. The circuit is implemented by Taiwan Semiconductor Manufacturing Company in 0.35 £gm 2-poly 4-metal CMOS process technology. The potential detection precision of a micro-balance using the forward generator is assessed by connecting test chips to an evaluation PCB with commercial piezo crystals providing a known resonance frequency for testing. National Instruments¡¦ LABVIEW is used to record the data output, and MATLAB to analyze the results. A minimum detection accuracy of 1 kHz is demonstrated with this setup.