In the field of the industrial automatic control, both MCU (Micro Control Unit) and PLC (Programmable Logic Controller) are widely being used in DCS (Distributed Control System). Since MCU can provide complex process scheduling, accurate timing control and PLC has the advantages of easy programming and maintaining. However, the control programs of the MCU are hard to design and maintain. Identically, the poor signal processing ability, high cost and the restrictive functions are the major defects of PLC. In order to solve the drawbacks described above in MCU and PLC, we provide a PLC-like interface for users to access the devices and set the registers of MCU. Likewise, designers can develop the control program via Event-table-driven modules. On the other hand, our main goal of DCS is to quickly construct the distributed N level network topology based on Modbus protocol, which is efficient and reliable. Therefore, we bring up a data collection method and Slave-to-Slave strategy so as to distribute the master loading, reduce the package transmission times and improve the real-time latency. In conclusion, our research results not only congregate the benefits of MCU and PLC but provide an environment to quickly construct and conveniently monitor DCS, which meets the time-to-market demands.

Power Consumption in VLSI (Very Large Scale Integrated) circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. Several of these applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used in these cases, but at such a low supply voltage these circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this thesis we implement and test a robust sub-threshold design flow which uses circuit level PVT compensation to stabilize circuit performance. This is done by dynamic modulation of the delay of a representative signal in the circuit and then phase locking it with an external reference signal. We design and fabricate a sub-threshold wireless BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps over a distance of 1000m. In addition to the sub-threshold implementation, we implement the BFSK transmitter using a standard cell methodology on the same die operating at super-threshold voltages on a different voltage domain. Experiments using the fabricated die show that the sub-threshold circuit consumes 19.4x lower power than the traditional standard cell based implementation.

The paper proposes a model of detection for voltages and harmonics using wavelet-probabilistic network (WPN). WPN is a two-layer structure, containing the wavelet layer and probabilistic network. It uses the wavelet transformation (WT) and probabilistic neural network (PNN) to analyze distorted waves and classify tasks. In this thesis, the field programmable gate array (FPGA) is employed for the hardware realization of WPN. In the implementation process, by the use of the hardware description language, the WPN algorithm has been embedded into the FPGA chip. Firstly, we divide the mathematical formula of basic WPN algorithm into several parts in order to set up each module individually, then we integrate all modules to complete the design of basic WPN algorithm with digital circuits by the bottom-up process.

Reconfigurable computing systems require supports from powerful computer aided design tools to help users developing the interactions between software programs and hardware circuits. The placement and routing support for reconfigurable processing units is also the key to the efficiency of the computing system. In this thesis, we implemented the placement and routing tool for the FMRPU (Fine-grain Multi-context Reconfigurable Processing Unit). The routing resource among the Logic Arrays supports only 8-bit aligned data width, so the routing of the FMRPU can¡¦t completely imitate from the pattern used by LUT-based routing. Thus we proposed an operation-based design model which accepts a data flow graph that describes the operations of the circuit. After compressing the graph, the tool uses Simulated Annealing algorithm with either Maze Route or Center-of-Gravity Route to map the compressed graph into FMRPU. Through the placement and routing tool we implemented, we have successfully mapped several algorithms used in multi-media applications, such as FFT and DCT, into FMRPU.

This thesis presents the CMOS integer-N frequency synthesizer for 2 GHz 802.11 WLAN applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, and a pulse-swallow counter. In pulse-swallow counter, we use less numbers of transistors divide-by-2/3 prescaler to work in high frequency in order to reduce power consumption. We complete the design of pulse-swallow counter for 2-GHz (seven channels) and the 5-GHz (four channels) application. The average power consumption of pulse-swallow counter is 2.49 mW and 2.98 mW for 2-GHz and 5-GHz application respectively. We use Verilog-A language to complete VCO behavior model for frequency synthesizer and utilize the Spectre simulation results justify the feasibility of our proposed frequency synthesizer. The total power consumption of frequency synthesizer is 3.432mW and 4.673mW for 2-GHz and 5-GHz frequency synthesizer, respectively.

Power Consumption in VLSI (Very Large Scale Integrated) circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. Several of these applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used in these cases, but at such a low supply voltage these circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this thesis we implement and test a robust sub-threshold design flow which uses circuit level PVT compensation to stabilize circuit performance. This is done by dynamic modulation of the delay of a representative signal in the circuit and then phase locking it with an external reference signal. We design and fabricate a sub-threshold wireless BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps over a distance of 1000m. In addition to the sub-threshold implementation, we implement the BFSK transmitter using a standard cell methodology on the same die operating at super-threshold voltages on a different voltage domain. Experiments using the fabricated die show that the sub-threshold circuit consumes 19.4x lower power than the traditional standard cell based implementation.

Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer high performance given tight constraints on power and chip area. Field programmable arrays utilizing floating-gate technology are one possible solution to analog design. It offers the advantages of analog processing with the additional advantage of reconfigurability, giving the designer the ability to test new analog designs without costly and time-consuming fabrication and test cycles. In this work, a new interface for FPAA's is demonstrated called Sim2spice, with which users can design signal processing systems in Matlab Simulink and compile them to SPICE circuit netlists. These netlists can be further compiled with a tool called GRASPER to a switch list for programming on an FPAA chip. Example library elements are shown, along with some compiled systems such as filters and vector-matrix multipliers. One particularly compelling application of reconfigurable analog design is the field of neuromorphic circuits, which aims to reproduce the basic functional characteristics of biological neurons and synapses in analog integrated circuit technology. Simulink libraries have been built to allow designers to build neuromorphic systems on several FPAAs that have been developed expressly for the purpose of building neurons and connecting them in networks with synapses. Several possible dynamically learning synapses have also been explored.

Thesis (M.S.)--State University of New York at Binghamton, Department of Electrical and Computer Engineering. / Includes bibliographical references (p. 55-56).

Thesis (M.S.)--University of North Texas, August, 2009. / Title from title page display. Includes bibliographical references.

Thesis (M.S.)--West Virginia University, 2008. / Title from document title page. Document formatted into pages; contains ix, 107 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 101-107).