Previsualization is a class of techniques for creating approximate previews of a movie sequence in order to visualize a scene prior to shooting it on the set. Often these techniques are used to convey the artistic direction of the story in terms of cinematic elements, such as camera movement, angle, lighting, dialogue, and character motion. Essentially, a movie director uses previsualization (previs) to convey movie visuals as he sees them in his "minds-eye". Traditional methods for previs include hand-drawn sketches, Storyboards, scaled models, and photographs, which are created by artists to convey how a scene or character might look or move. A recent trend has been to use 3D graphics applications such as video game engines to perform previs, which is called 3D previs. This type of previs is generally used prior to shooting a scene in order to choreograph camera or character movements. To visualize a scene while being recorded on-set, directors and cinematographers use a technique called On-set previs, which provides a real-time view with little to no processing. Other types of previs, such as Technical previs, emphasize accurately capturing scene properties but lack any interactive manipulation and are usually employed by visual effects crews and not for cinematographers or directors. This dissertation's focus is on creating a new method for interactive visualization that will automatically capture the on-set lighting and provide interactive manipulation of cinematic elements to facilitate the movie maker's artistic expression, validate cinematic choices, and provide guidance to production crews. Our method will overcome the drawbacks of the all previous previs methods by combining photorealistic rendering with accurately captured scene details, which is interactively displayed on a mobile capture and rendering platform. This dissertation describes a new hardware and software previs framework that enables interactive visualization of on-set post-production elements. A three-tiered framework, which is the main contribution of this dissertation is; 1) a novel programmable camera architecture that provides programmability to low-level features and a visual programming interface, 2) new algorithms that analyzes and decomposes the scene photometrically, and 3) a previs interface that leverages the previous to perform interactive rendering and manipulation of the photometric and computer generated elements. For this dissertation we implemented a programmable camera with a novel visual programming interface. We developed the photometric theory and implementation of our novel relighting technique called Symmetric lighting, which can be used to relight a scene with multiple illuminants with respect to color, intensity and location on our programmable camera. We analyzed the performance of Symmetric lighting on synthetic and real scenes to evaluate the benefits and limitations with respect to the reflectance composition of the scene and the number and color of lights within the scene. We found that, since our method is based on a Lambertian reflectance assumption, our method works well under this assumption but that scenes with high amounts of specular reflections can have higher errors in terms of relighting accuracy and additional steps are required to mitigate this limitation. Also, scenes which contain lights whose colors are a too similar can lead to degenerate cases in terms of relighting. Despite these limitations, an important contribution of our work is that Symmetric lighting can also be leveraged as a solution for performing multi-illuminant white balancing and light color estimation within a scene with multiple illuminants without limits on the color range or number of lights. We compared our method to other white balance methods and show that our method is superior when at least one of the light colors is known a priori.

O uso de pequenos satélites tem aumentado substancialmente nos últimos anos devido ao custo reduzido de desenvolvimento e lançamento, assim como pela flexibilidade oferecida pela utilização de componentes comerciais. Este trabalho propõe o projeto e a implementação de uma plataforma para teste, controle e qualificação de circuitos integrados (Integrated Circuits, CIs) comerciais e customizados para uso em aplicações espaciais. Esta plataforma flexível pode ser ajustada a uma gama de dispositivos e interfaces, e reduz os esforços de integração desses componentes e, portanto, acelera o desenvolvimento de todo o projeto. O sistema proposto é sintetizado em um tecnologia de Arranjo de Portas Programáveis em Campo (Field Programmable Gate Array) baseado em memória Flash, que, apesar de não ser classificado para uso aeroespacial, testes demonstram a viabilidade de seu uso. Este sistema adaptável permite o controle de novas cargas-úteis e softcores para o teste e validação antes da sua aplicação em voo. A comunicação com dispositivos é feita através de protocolos préimplementados. Os resultados de testes funcionais in loco sugerem a possibilidade de aplicação desta plataforma para uso em Cubesats. A primeira aplicação desta plataforma foi no teste do controle da placa de carga-útil do NanoSatC-BR1, o primeiro nanossatélite científico brasileiro, lançado em órbita em 2014. / The number of small satellites has substantially increased in the last years due to reduced development and launching costs, as well as due to the flexibility brought by the usage of commercial off the shelf components. This work purposes the design and implementation of a platform for test, control and qualification of commercial and customized integrated circuits for space applications. This flexible platform can be adjusted to control a wide range of devices and interfaces, and is intended to reduce the integration difficulties, resulting in the speed up of some of the project stages. The platform is synthesized in a Flash-based Field Programmable Gate Array technology. The target device is not qualified for aerospace projects. Nevertheless, previous radiation tests demonstrated its hardness for space missions. The system is adaptable and makes it possible to control, test and validate new payloads and softcores before flight. The communication between devices is done through pre-implemented protocols. Functional tests suggested the possibility to apply the platform in Cubesats projects. The first application of this platform was in the NanoSatC-BR1, the first Brazilian scientific nanosatellite, to test the controller of the payload board.

Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017. / The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly reduced communication system performance. One of the effects of these constraints is the limitation on the type of channel coding technique that can be implemented in these communication systems. Another limiting factor on nano-satellite communication systems is the limited space available due to the compact nature of these satellites, where numerous complex systems are tightly packed into a space as small as 10x10x10cm. With the miniaturisation of Integrated-Circuit (IC) technology and the affordability of Field-Programmable-Gate-Arrays (FPGAs) with reduced power consumption, complex circuits can now be implemented within small form factors and at low cost. This thesis describes the design, implementation and cost evaluation of a ½-rate convolutional encoder and the corresponding Viterbi decoder on an FPGA for nano-satellites applications. The code for the FPGA implementation is described in VHDL and implemented on devices from the Artix7 (Xilinx), Cyclone V (Intel-fpga), and Igloo2 (Microsemi) families. The implemented channel code has a coding gain of ~3dB at a BER of 10-3. It can be noted that the implementation of the encoder is quite straightforward and that the main challenge is in the implementation of the decoder.

Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. / Includes bibliographical references (leaves 99-100). / This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. / This thesis investigates the feasibility of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architecture is designed to allow smaller segments of the device to be individually reconfigured while the remainder of the device continues to operate. This document describes the design, implementation, simulation, and benchmarking of a five-socket modular DSP architecture and compares the results to the performance of alternative digital signal processing methods, particularly that of software DSP subroutines run on a PowerPC processor. The result is a highly flexible architecture that supports the use of timing verified hardware subroutines that could be partially reconfigured onto the FPGA within 3ms. The highly parallel processing power of the FPGA design yields a performance of 5.825 billion multiply and accumulate operations per second while simulated running at 72.8MHz, more than 76 times faster than similar calculations measured on a MPC7410 processor. / by Justin D. McBride. / M.Eng.and S.B.

Tang Wai Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 40-41). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Algorithms --- p.3 / Chapter 2.1 --- REWIRE --- p.5 / Chapter 2.2 --- RAMFIRE --- p.7 / Chapter 2.3 --- GBAW --- p.8 / Chapter 3 --- FPGA Technology Mapping --- p.11 / Chapter 3.1 --- Problem Definition --- p.13 / Chapter 3.2 --- Network-flow-based Algorithms for FPGA Technology Mapping --- p.16 / Chapter 3.2.1 --- FlowMap --- p.16 / Chapter 3.2.2 --- FlowSYN --- p.21 / Chapter 3.2.3 --- CutMap --- p.22 / Chapter 4 --- LUT Minimization by Rewiring --- p.24 / Chapter 4.1 --- Greedy Decision Heuristic for LUT Minimization --- p.27 / Chapter 4.2 --- Experimental Result --- p.28 / Chapter 5 --- Conclusion --- p.38 / Bibliography --- p.40

Mak Sui Tung Terrence. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 132-142). / Abstracts in English and Chinese. / Abstract --- p.i / List of Tables --- p.iv / List of Figures --- p.v / Acknowledgements --- p.ix / Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Bioinformatics --- p.1 / Chapter 1.2 --- Neural Prosthetics --- p.4 / Chapter 1.3 --- Learning in Uncertainty --- p.5 / Chapter 1.4 --- The Field Programmable Gate Array (FPGAs) --- p.7 / Chapter 1.5 --- Scope of the Thesis --- p.10 / Chapter 2. --- A Hybrid GA-DP Approach for Searching Equivalence Sets --- p.14 / Chapter 2.1 --- Introduction --- p.16 / Chapter 2.2 --- Equivalence Set Criterion --- p.18 / Chapter 2.3 --- Genetic Algorithm and Dynamic Programming --- p.19 / Chapter 2.3.1 --- Genetic Algorithm Formulation --- p.20 / Chapter 2.3.2 --- Bounded Mutation --- p.21 / Chapter 2.3.3 --- Conditioned Crossover --- p.22 / Chapter 2.3.4 --- Implementation --- p.22 / Chapter 2.4 --- FPGAs Implementation of GA-DP --- p.24 / Chapter 2.4.1 --- System Overview --- p.25 / Chapter 2.4.2 --- Parallel Computation for Transitive Closure --- p.26 / Chapter 2.4.3 --- Genetic Operation Realization --- p.28 / Chapter 2.5 --- Discussion --- p.30 / Chapter 2.6 --- Limitation and Future Work --- p.33 / Chapter 2.7 --- Conclusion --- p.34 / Chapter 3. --- An FPGA-based Architecture for Maximum-Likelihood Phylogeny Evaluation --- p.35 / Chapter 3.1 --- Introduction --- p.36 / Chapter 3.2 --- Maximum-Likelihood Model --- p.39 / Chapter 3.3 --- Hardware Mapping for Pruning Algorithm --- p.41 / Chapter 3.3.1 --- Related Works --- p.41 / Chapter 3.3.2 --- Number Representation --- p.42 / Chapter 3.3.3 --- Binary Tree Representation --- p.43 / Chapter 3.3.4 --- Binary Tree Traversal --- p.45 / Chapter 3.3.5 --- Maximum-Likelihood Evaluation Algorithm --- p.46 / Chapter 3.4 --- System Architecture --- p.49 / Chapter 3.4.1 --- Transition Probability Unit --- p.50 / Chapter 3.4.2 --- State-Parallel Computation Unit --- p.51 / Chapter 3.4.3 --- Error Computation --- p.54 / Chapter 3.5 --- Discussion --- p.56 / Chapter 3.5.1 --- Hardware Resource Consumption --- p.56 / Chapter 3.5.2 --- Delay Evaluation --- p.57 / Chapter 3.6 --- Conclusion --- p.59 / Chapter 4. --- Field Programmable Gate Array Implementation of Neuronal Ion Channel Dynamics --- p.61 / Chapter 4.1 --- Introduction --- p.62 / Chapter 4.2 --- Background --- p.63 / Chapter 4.2.1 --- Analog VLSI Model for Hebbian Synapse --- p.63 / Chapter 4.2.2 --- A Unifying Model of Bi-directional Synaptic Plasticity --- p.64 / Chapter 4.2.3 --- Non-NMDA Receptor Channel Regulation --- p.65 / Chapter 4.3 --- FPGAs Implementation --- p.65 / Chapter 4.3.1 --- FPGA Design Flow --- p.65 / Chapter 4.3.2 --- Digital Model of NMD A and AMPA receptors --- p.65 / Chapter 4.3.3 --- Synapse Modification --- p.67 / Chapter 4.4 --- Results --- p.68 / Chapter 4.4.1 --- Simulation Results --- p.68 / Chapter 4.5 --- Discussion --- p.70 / Chapter 4.6 --- Conclusion --- p.71 / Chapter 5. --- Continuous-Time and Discrete-Time Inference Networks for Distributed Dynamic Programming --- p.72 / Chapter 5.1 --- Introduction --- p.74 / Chapter 5.2 --- Background --- p.77 / Chapter 5.2.1 --- Markov decision process (MDPs) --- p.78 / Chapter 5.2.2 --- Learning in the MDPs --- p.80 / Chapter 5.2.3 --- Bellman Optimal Criterion --- p.80 / Chapter 5.2.4 --- Value Iteration --- p.81 / Chapter 5.3 --- A Computational Framework for Continuous-Time Inference Network --- p.82 / Chapter 5.3.1 --- Binary Relation Inference Network --- p.83 / Chapter 5.3.2 --- Binary Relation Inference Network for MDPs --- p.85 / Chapter 5.3.3 --- Continuous-Time Inference Network for MDPs --- p.87 / Chapter 5.4 --- Convergence Consideration --- p.88 / Chapter 5.5 --- Numerical Simulation --- p.90 / Chapter 5.5.1 --- Example 1: Random Walk --- p.90 / Chapter 5.5.2 --- Example 2: Random Walk on a Grid --- p.94 / Chapter 5.5.3 --- Example 3: Stochastic Shortest Path Problem --- p.97 / Chapter 5.5.4 --- Relationships Between λ and γ --- p.99 / Chapter 5.6 --- Discrete-Time Inference Network --- p.100 / Chapter 5.6.1 --- Results --- p.101 / Chapter 5.7 --- Conclusion --- p.102 / Chapter 6. --- On Distributed g-Learning Network --- p.104 / Chapter 6.1 --- Introduction --- p.105 / Chapter 6.2 --- Distributed Q-Learniing Network --- p.108 / Chapter 6.2.1 --- Distributed Q-Learning Network --- p.109 / Chapter 6.2.2 --- Q-Learning Network Architecture --- p.111 / Chapter 6.3 --- Experimental Results --- p.114 / Chapter 6.3.1 --- Random Walk --- p.114 / Chapter 6.3.2 --- The Shortest Path Problem --- p.116 / Chapter 6.4 --- Discussion --- p.120 / Chapter 6.4.1 --- Related Work --- p.121 / Chapter 6.5 --- FPGAs Implementation --- p.122 / Chapter 6.5.1 --- Distributed Registering Approach --- p.123 / Chapter 6.5.2 --- Serial BRAM Storing Approach --- p.124 / Chapter 6.5.3 --- Comparison --- p.125 / Chapter 6.5.4 --- Discussion --- p.127 / Chapter 6.6 --- Conclusion --- p.128 / Chapter 7. --- Summary --- p.129 / Bibliography --- p.132 / Appendix / Chapter A. --- Simplified Floating-Point Arithmetic --- p.143 / Chapter B. --- "Logarithm, Exponential and Division Implementation" --- p.144 / Chapter B.1 --- Introduction --- p.144 / Chapter B.2 --- Approximation Scheme --- p.145 / Chapter B.2.1 --- Logarithm --- p.145 / Chapter B.2.2 --- Exponentiation --- p.147 / Chapter B.2.3 --- Division --- p.148 / Chapter C. --- Analog VLSI Implementation --- p.150 / Chapter C.1 --- Site Function --- p.150 / Chapter C.1.1 --- Multiplication Cell --- p.150 / Chapter C.2 --- The Unit Function --- p.153 / Chapter C.3 --- The Inference Network Computation --- p.154 / Chapter C.4 --- Layout --- p.157 / Chapter C.5 --- Fabrication --- p.159 / Chapter C.5.1 --- Testing and Characterization --- p.161

(I) Architectural revisions: Probably due to historical reasons, programmable switches on conventional FPGA architectures are divided into two kinds of substructures: Connection boxes (C-boxes) and Switch boxes (S-boxes), where C-boxes are used to connect logic/pad pins with their crossing wire segments, and S-boxes are used to connect wire segments of surrounding routing channels. In this work, we will challenge if this divided C- and S-boxes structure is really necessary and will explore a new experimental architecture which adopts only one kind of switching components - Connection-Switch boxes (CS-boxes). Extensive experiments are conducted on MCNC benchmark circuits to justify its architectural performance impacts. The results show that this CS-box based FPGA outperforms the conventional FPGA in terms of channel width, circuit delay, and segment usage. Besides an over 20% drastic dropping in the total number of manufactured switches needed, circuit delay performance is improved by 10% under the usage of the same pin assignments and router. / (II) New EDA technique/flow: By applying circuit rewirings, logic perturbations can be carried out by shifting logic resources from perhaps costly Look-Up-Table (LUT) external to cost-free LUT internal areas, or from critical to non-critical paths. This work presents a simple, while effective and low-overhead postlayout logic perturbation scheme for improving LUT-based FPGA routings without altering placements. A rewiring-based logic perturbation technique is used to improve upon a timing-driven FPGA P&R tool - TVPR. Compared with the already high-quality pure TVPR results, our approach reduces critical path delay by up to 31.74% (avg. 11%) without disturbing the placement or sacrificing chip areas, where only 4% of the nets are perturbed in our scheme. The complexity of our algorithm is linear in the total number of nets of the circuit. The experimental results show that the CPU time used by the rewiring engine is only 5% of the total time consumed by the placement and routing of TVPR. / Based on these studies, we believe the prospect for FPGA performance improvement is still quite profound in both architectural and EDA aspects. On the EDA technique, we have also performed logic perturbations to improve both the technology mapping and routing to investigate the effectiveness of the logic perturbation if applied in a larger context. The results show that a best technology mapping is not always leading to a best final routing, which seems to suggest that an ideal FPGA EDA flow should consider more on trade-offs between different stages. To the best of our knowledge, this is the first work exploring the power of logic perturbations applied for multiple physical stages for LUT-based FPGAs. The encouraging hardware improvement shown in our proposed CS-box based FPGAs seems to suggest a new design direction for FPGA routing architectures. / With the advent of deep submicron technologies, the extreme high design and mask costs incurred for ASICs have made FPGAs an increasingly popular hardware implementation option. However, it has been shown that the programmable routing structure underlined contributes over 60% of the signal delay and as high as 90% of the total chip area. As a result, current FPGAs still cannot meet performance requirements of many high-end applications. To attack this issue, we propose new solutions along the two major tracks: (I) architectural revisions (hardware) and (II) new EDA technique/flow (software). / Zhou Lin. / "October 2007." / Adviser: Yu-Liang Wu. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4953. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 101-108). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Leung Ka Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves [85]-90). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / List of Figures --- p.ix / List of Tables --- p.xi / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.3 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Outline --- p.4 / Chapter 2 --- Cryptography --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Foundations --- p.6 / Chapter 2.3 --- Secret Key Cryptosystems --- p.8 / Chapter 2.4 --- Public Key Cryptosystems --- p.9 / Chapter 2.4.1 --- One-way Function --- p.10 / Chapter 2.4.2 --- Certification Authority --- p.10 / Chapter 2.4.3 --- Discrete Logarithm Problem --- p.11 / Chapter 2.4.4 --- RSA vs. ECC --- p.12 / Chapter 2.4.5 --- Key Exchange Protocol --- p.13 / Chapter 2.4.6 --- Digital Signature --- p.14 / Chapter 2.5 --- Secret Key vs. Public Key Cryptography --- p.16 / Chapter 2.6 --- Summary --- p.18 / Chapter 3 --- Mathematical Background --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Groups and Fields --- p.19 / Chapter 3.3 --- Finite Fields --- p.21 / Chapter 3.4 --- Modular Arithmetic --- p.21 / Chapter 3.5 --- Polynomial Basis --- p.21 / Chapter 3.6 --- Optimal Normal Basis --- p.22 / Chapter 3.6.1 --- Addition --- p.23 / Chapter 3.6.2 --- Squaring --- p.24 / Chapter 3.6.3 --- Multiplication --- p.24 / Chapter 3.6.4 --- Inversion --- p.30 / Chapter 3.7 --- Summary --- p.33 / Chapter 4 --- Literature Review --- p.34 / Chapter 4.1 --- Introduction --- p.34 / Chapter 4.2 --- Hardware Elliptic Curve Implementation --- p.34 / Chapter 4.2.1 --- Field Processors --- p.34 / Chapter 4.2.2 --- Curve Processors --- p.36 / Chapter 4.3 --- Software Elliptic Curve Implementation --- p.36 / Chapter 4.4 --- Summary --- p.38 / Chapter 5 --- Introduction to Elliptic Curves --- p.39 / Chapter 5.1 --- Introduction --- p.39 / Chapter 5.2 --- Historical Background --- p.39 / Chapter 5.3 --- Elliptic Curves over R2 --- p.40 / Chapter 5.3.1 --- Curve Addition and Doubling --- p.41 / Chapter 5.4 --- Elliptic Curves over Finite Fields --- p.44 / Chapter 5.4.1 --- Elliptic Curves over Fp with p>〉3 --- p.44 / Chapter 5.4.2 --- Elliptic Curves over F2n --- p.45 / Chapter 5.4.3 --- Operations of Elliptic Curves over F2n --- p.46 / Chapter 5.4.4 --- Curve Multiplication --- p.49 / Chapter 5.5 --- Elliptic Curve Discrete Logarithm Problem --- p.51 / Chapter 5.6 --- Public Key Cryptography --- p.52 / Chapter 5.7 --- Elliptic Curve Diffie-Hellman Key Exchange --- p.54 / Chapter 5.8 --- Summary --- p.55 / Chapter 6 --- Design Methodology --- p.56 / Chapter 6.1 --- Introduction --- p.56 / Chapter 6.2 --- CAD Tools --- p.56 / Chapter 6.3 --- Hardware Platform --- p.59 / Chapter 6.3.1 --- FPGA --- p.59 / Chapter 6.3.2 --- Reconfigurable Hardware Computing --- p.62 / Chapter 6.4 --- Elliptic Curve Processor Architecture --- p.63 / Chapter 6.4.1 --- Arithmetic Logic Unit (ALU) --- p.64 / Chapter 6.4.2 --- Register File --- p.68 / Chapter 6.4.3 --- Microcode --- p.69 / Chapter 6.5 --- Parameterized Module Generator --- p.72 / Chapter 6.6 --- Microcode Toolkit --- p.73 / Chapter 6.7 --- Initialization by Bitstream Reconfiguration --- p.74 / Chapter 6.8 --- Summary --- p.75 / Chapter 7 --- Results --- p.76 / Chapter 7.1 --- Introduction --- p.76 / Chapter 7.2 --- Elliptic Curve Processor with Serial Multiplier (p = 1) --- p.76 / Chapter 7.3 --- Projective verses Affine Coordinates --- p.78 / Chapter 7.4 --- Elliptic Curve Processor with Parallel Multiplier (p > 1) --- p.79 / Chapter 7.5 --- Summary --- p.80 / Chapter 8 --- Conclusion --- p.82 / Chapter 8.1 --- Recommendations for Future Research --- p.83 / Bibliography --- p.85 / Chapter A --- Elliptic Curves in Characteristics 2 and3 --- p.91 / Chapter A.1 --- Introduction --- p.91 / Chapter A.2 --- Derivations --- p.91 / Chapter A.3 --- "Elliptic Curves over Finite Fields of Characteristic ≠ 2,3" --- p.92 / Chapter A.4 --- Elliptic Curves over Finite Fields of Characteristic = 2 --- p.94 / Chapter B --- Examples of Curve Multiplication --- p.95 / Chapter B.1 --- Introduction --- p.95 / Chapter B.2 --- Numerical Results --- p.96

The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in the last thirty years, many of the best techniques have yet to find their way into embedded computers, and their failure can have a great potential for disrupting society. This dissertation presents some approaches to improve computer reliability using software and hardware techniques, and makes the following claims for novelty: innovative development of a toolchain and libraries to support extraction from dependent type checking in a theorem prover; conceptual design and deployment in reconfigurable hardware; an extension of static type-safety to hardware description language and FPGA level; elimination of legacy C code from the target and toolchain; a novel hardware error detection scheme is described and compared with conventional triple modular redundancy. The elimination of any user control of memory management promotes robustness against buffer overruns, and consequently prevents vulnerability to common Trojan techniques. The methodology identifies type punning as a key weakness of commonly encountered embedded languages such as C, in particular the extreme difficulty of determining if an array access is in bounds, or if dynamic memory has been properly allocated and released. A method of eliminating dependence on type-unsafe libraries is presented, in conjunction with code that has optionally been proved correct according to user-defined criteria. An appropriately defined subset of OCaml is chosen with support for the Coq theorem prover in mind, and then evaluated with a custom backend that supports behavioural Verilog, as well as a fixed execution unit and associated control store. Results are presented for this alternative platform for reliable embedded systems development that may be used in future industrial flows. To provide assurance of correct operation, the proven software needs to be executed in an environment where errors are checked and corrected in conjunction with appropriate exception processing in the event of an uncorrectable error. Therefore, the present author’s previously published error detection scheme based on dual-rail logic and self-checking checkers is further developed and compared with traditional N-modular redundancy.

Devido às necessidades do mundo moderno, os sistemas de automação têm aumentado sua complexidade, fazendo com que sejam desenvolvidas ferramentas de engenharia cada vez mais poderosas para modelá-los e analisá-los. Em sistemas de automação industrial, os Controladores Lógicos Programáveis (CLPs) têm sido amplamente empregados. Os CLPs são geralmente programados por meio da linguagem de programação Ladder, uma das cinco linguagens definidas pela IEC 61131-3. Entretanto, apesar da linguagem de programação Ladder ser flexível e de fácil aprendizado por parte dos usuários, ela apresenta limitações quanto à: detecção de erros no algoritmo de controle do sistema de automação; torna as modificações muito trabalhosas e não possibilita a simulação, análise de performance e análise operacional do sistema. Este trabalho de pesquisa apresenta o desenvolvimento e os testes da metodologia denominada MARPASI - Metodologia de Aplicação das Redes de Petri em Automação de Sistemas Industriais. Como o desenvolvimento da MARPASI foi efetuado baseado na teoria de Redes de Petri, este trabalho também apresenta uma revisão bibliográfica sobre o tema de aplicação de Redes de Petri para a programação de CLP. A MARPASI possibilita analisar um sistema de automação por meio das Redes de Petri e na geração da linguagem de programação Ladder. Portanto, o emprego da MARPASI contribui para a otimização do processo de engenharia de automação e também para a programação mais eficiente de CLPs. / Due to the needs of the modern world, the systems of automation have increased their complexity, forcing the development of ever more powerful engineering tolls to shape and analyse them. In systems of industrial automation, the Programmable Logic Controllers (PLCs), have been widely applies. The PLCs are generally programmed through the use of the Ladder programming language, one of the five languages defined by the IEC 61131-3. Unfortunately, while the Ladder programming language is flexible, and easily learned by its users, it evinces limitations concerning: error detection in the control algorithm of the automation system: makes modifications very laborious and does not allow any simulation, performance analysis and operational systems analysis. This study presents the development and tests of the methodology denominated as MARPASI - Methodology of the application of Petri Net in the automation of industrial systems. Since the development of MARPASI was made based on Petri Net Theory, this study also presents a bibliographic review about the theme of the application of Petri Net for the programming of PLC. MARPASI makes it possible to analyse a system of automation through Petri Net and in the generation of the Ladder programming language. Because of these, the utilization of MARPASI contributes for capacities, the optimization of automation engineering processes, and also for a more efficient programming of the PLCs.