In this thesis, a MP3 audio decoder has been designed as System-on-a-Chip using hardware/software co-design techniques. The MP3 audio decoder was built on a fast prototyping platform as ARM Integrator. The hardware architecture was built on the LEON2 SoC architecture, which contained an open source SPARC-V8 architecture compatible processor and an AMBA bus. Because MP3 decoding process was very computation-intensive for software-only decoder to decode in real-time on the LEON2 architecture, an IMDCT and poly phase synthesis filter bank hardware combined core pre-designed as an AMBA compatible core from our lab was reused and integrated. Besides integrating the IP, the MP3 decoding process was changed to use integer calculations instead of floating-point ones. In order to fast prototype LEON2 successfully on ARM Integrator, some modification of the LEON2 SoC hardware architecture was also made for example adding FIFO, modifying the memory controller, etc.

The goal of the thesis is to design a development board that may be used for embedded systems prototyping. The board's key parts are an ARM-Cortex-based microcontroller and a FPGA programmable circuit. The platform is designed with .NET Micro Framework support in mind. The thesis contains specifications of the development board, describes the design process as well as the task of .NET Micro Framework porting and the establishment of communication bus between the FPGA and microcontroller circuits. The thesis is concluded by a set of demonstration examples which outline how to develop new applications for the designed platform.

Cette thèse est élaborée en cotutelle entre l’université Badji Mokhtar (Laboratoire LERICA) et l’université de bourgogne (Laboratoire LE2I, UMR CNRS 5158). Elle constitue une contribution à l’étude et l’implantation de l’encodeur H.264/AVC. Durent l’évolution des normes de compression vidéo, une réalité sure est vérifiée de plus en plus : avoir une bonne performance du processus de compression nécessite l’élaboration d’équipements beaucoup plus performants en termes de puissance de calcul, de flexibilité et de portabilité et ceci afin de répondre aux exigences des différents traitements et satisfaire au critère « Temps Réel ». Pour assurer un temps réel pour ce genre d’applications, une solution reste possible est l’utilisation des systèmes sur puce (SoC) ou bien des systèmes multiprocesseurs sur puce (MPSoC) implantés sur des plateformes reconfigurables à base de circuit FPGA. L’objective de cette thèse consiste à l’étude et l’implantation des algorithmes de traitement des signaux et images et en particulier la norme H.264/AVC, et cela dans le but d’assurer un temps réel pour le cycle codage-décodage. Nous utilisons deux plateformes FPGA de Xilinx (ML501 et XUPV5). Dans la littérature, il existe déjà plusieurs implémentations du décodeur. Pour l’encodeur, malgré les efforts énormes réalisés, il reste toujours du travail pour l’optimisation des algorithmes et l’extraction des parallélismes possibles surtout avec une variété de profils et de niveaux de la norme H.264/AVC.Dans un premier temps de cette thèse, nous proposons une implantation matérielle d’un contrôleur mémoire spécialement pour l’encodeur H.264/AVC. Ce contrôleur est réalisé en ajoutant, au contrôleur mémoire DDR2 des deux plateformes de Xilinx, une couche intelligente capable de calculer les adresses et récupérer les données nécessaires pour les différents modules de traitement de l’encodeur. Ensuite, nous proposons des implantations matérielles (niveau RTL) des modules de traitement de l’encodeur H.264. Sur ces implantations, nous allons exploiter les deux principes de parallélisme et de pipelining autorisé par l’encodeur en vue de la grande dépendance inter-blocs. Nous avons ainsi proposé plusieurs améliorations et nouvelles techniques dans les modules de la chaine Intra et le filtre anti-blocs. A la fin de cette thèse, nous utilisons les modules réalisés en matériels pour la l’implantation Matérielle/logicielle de l’encodeur H.264/AVC. Des résultats de synthèse et de simulation, en utilisant les deux plateformes de Xilinx, sont montrés et comparés avec les autres implémentations existantes / This thesis has been carried out in joint supervision between the Badji Mokhtar University (LERICA Laboratory) and the University of Burgundy (LE2I laboratory, UMR CNRS 5158). It is a contribution to the study and implementation of the H.264/AVC encoder. The evolution in video coding standards have historically demanded stringent performances of the compression process, which imposes the development of platforms that perform much better in terms of computing power, flexibility and portability. Such demands are necessary to fulfill requirements of the different treatments and to meet "Real Time" processing constraints. In order to ensure real-time performances, a possible solution is to made use of systems on chip (SoC) or multiprocessor systems on chip (MPSoC) built on platforms based reconfigurable FPGAs. The objective of this thesis is the study and implementation of algorithms for signal and image processing (in particular the H.264/AVC standard); especial attention was given to provide real-time coding-decoding cycles. We use two FPGA platforms (ML501 and XUPV5 from Xilinx) to implement our architectures. In the literature, there are already several implementations of the decoder. For the encoder part, despite the enormous efforts made, work remains to optimize algorithms and extract the inherent parallelism of the architecture. This is especially true with a variety of profiles and levels of H.264/AVC. Initially, we proposed a hardware implementation of a memory controller specifically targeted to the H.264/AVC encoder. This controller is obtained by adding, to the DDR2 memory controller, an intelligent layer capable of calculating the addresses and to retrieve the necessary data for several of the processing modules of the encoder. Afterwards, we proposed hardware implementations (RTL) for the processing modules of the H.264 encoder. In these implementations, we made use of principles of parallelism and pipelining, taking into account the constraints imposed by the inter-block dependency in the encoder. We proposed several enhancements and new technologies in the channel Intra modules and the deblocking filter. At the end of this thesis, we use the modules implemented in hardware for implementing the H.264/AVC encoder in a hardware/software design. Synthesis and simulation results, using both platforms for Xilinx, are shown and compared with other existing implementations

La investigación realizada a los sistemas de seguridad electrónica de edificios, plantea como objetivo principal el reconocimiento de tres gestos de un lenguaje corporal del personal de vigilancia, y la consecuente activación de alarma en forma automática. Inicialmente se realizó una encuesta dirigida a las administraciones y personal de edificios, para saber cuales eran las ocurrencias que vulneraban la seguridad de un edificio multifamiliar, luego se observaron y analizaron las imágenes capturadas por una cámara de vigilancia ubicada en la recepción, identificando las ocurrencias más vulnerables y gestos asociados a dichos eventos; se seleccionaron tres gestos que en forma inconsciente realizaba el personal de vigilancia ante dichas situaciones. A determinados cuadros que comprenden estas imágenes se le aplicaron técnicas de procesamiento espacial, con ayuda de una iluminación artificial que era más intensa en la parte posterior del sujeto de análisis, consiguiéndose la definición de una silueta binarizada en el entorno Matlab, técnicas como selección del plano rojo, plano de bits más significativo, invertir imagen y transformaciones morfológicas tipo cerradura, definieron una silueta que ayudó a desarrollar un algoritmo matemático para generar una señal eléctrica en el puerto serial USB del ordenador, donde se conectó físicamente una plataforma de hardware Arduino que activa la alarma. La elección de esta plataforma se debió a que Matlab cuenta con un grupo de instrucciones para Arduino, con el objetivo de lograr una comunicación sincronizada entre ordenador e interface. Las técnicas utilizadas reconocieron 62,5% de los eventos descritos en las encuestas realizadas y que no son mencionadas en temas de investigación similar. Para lograr el objetivo fue necesario analizar un cuadro por segundo. The research poses as their main objective the three gestures recognition of a body language of surveillance personnel and the consequent activation of alarm automatically. It was initially carried out a survey of the administration and the offices of the buildings to know which were the occurrences that violate the security of a multi-family building, then were observed and analyzed images captured by a surveillance camera located in the reception, identifying the most vulnerable occurrences and gestures associated with these events; were selected three gestures that unconsciously performs surveillance personnel before such situations; to certain pictures that comprise these images were applied spatial processing techniques, with the help of an artificial lighting that was more intense in the back of the subject of analysis, getting the definition of a silhouette binarized in the Matlab environment, techniques such as plane selection red, more significant bit plane, to invest an image and convolution close type, defined a silhouette that allowed to develop a mathematical algorithm that generated an electrical signal in USB serial port of the computer, where it is physically connected a hardware platform Arduino that active the alarm.This platform choice is due to the fact that Matlab has a group of instructions for Arduino, achieving an orderly communication between computer and interface. The techniques used recognized 62.5 % of the events described in the surveys carried out and which aren’t mentioned in similar research topics. To achieve the objective was necessary to analyze a picture per second.